公开(公告)号：US20240088099A1

公开(公告)日：2024-03-14

申请号：US18215681

申请日：2023-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Divya Madapusi Srinivas PRASAD ,  Vignesh ADHINARAYANAN ,  Michael IGNATOWSKI ,  Hyung-Dong LEE

IPC: H01L25/065 ,  G11C11/4097 ,  H01L25/18

CPC classification number: H01L25/0657 ,  G11C11/4097 ,  H01L25/18 ,  H01L2225/06555

Abstract: Memory stacks having substantially vertical bitlines, and chip packages having the same, are disclosed herein. In one example, a memory stack is provided that includes a first memory IC die and a second memory IC die. The second memory IC die is stacked on the first memory IC die. Bitlines are routed through the first and second IC dies in a substantially vertical orientation. Wordlines within the first memory IC die are oriented orthogonal to the bitlines.

公开(公告)号：US20240395289A1

公开(公告)日：2024-11-28

申请号：US18671854

申请日：2024-05-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Vignesh ADHINARAYANAN ,  Hyung-Dong LEE ,  Bradford BECKMANN ,  Seyedmohammad SEYEDZADEHDELCHEH ,  Sergey BLAGODUROV

IPC: G11C5/02 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: Integrated circuit (IC) memory devices and methods for fabricating the same are provided. In one example, an integrated circuit (IC) memory device is provided that includes a substrate, at least two or more memory (IC) dies, and a non-memory IC die integrated in a chip package. The memory (IC) dies are stacked on the substrate to form a memory die stack. The non-memory IC die contains row segmentation logic having an output routed to corresponding wordline drivers of the memory IC dies through vertical wiring passing through the memory die stack.