公开(公告)号：US20240088099A1

公开(公告)日：2024-03-14

申请号：US18215681

申请日：2023-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Divya Madapusi Srinivas PRASAD ,  Vignesh ADHINARAYANAN ,  Michael IGNATOWSKI ,  Hyung-Dong LEE

IPC: H01L25/065 ,  G11C11/4097 ,  H01L25/18

CPC classification number: H01L25/0657 ,  G11C11/4097 ,  H01L25/18 ,  H01L2225/06555

Abstract: Memory stacks having substantially vertical bitlines, and chip packages having the same, are disclosed herein. In one example, a memory stack is provided that includes a first memory IC die and a second memory IC die. The second memory IC die is stacked on the first memory IC die. Bitlines are routed through the first and second IC dies in a substantially vertical orientation. Wordlines within the first memory IC die are oriented orthogonal to the bitlines.

公开(公告)号：US20240088098A1

公开(公告)日：2024-03-14

申请号：US18199837

申请日：2023-05-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Divya Madapusi Srinivas PRASAD ,  Niti MADAN ,  Michael IGNATOWSKI ,  Hyung-Dong LEE

IPC: H01L25/065 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H10B80/00 ,  H01L2225/06503

Abstract: Disclosed wherein stacked memory dies that utilize a mix of high and low operational temperature memory and non-volatile based memory dies, and chip packages containing the same. High temperature memory dies, such as those using non-volatile memory (NVM) technologies are in a memory stack with low temperature memory dies, such as those having volatile memory technologies. In some cases, the high temperature memory technologies could be used together, in some cases, on the same IC die as logic circuitry. In one example, a memory stack is provided that include a first memory IC die having high temperature memory circuitry, such as non-volatile memory, stacked below a second memory IC die. The second memory IC die has high temperature memory circuitry, such as volatile memory circuitry.

公开(公告)号：US20240087632A1

公开(公告)日：2024-03-14

申请号：US18216501

申请日：2023-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Divya Madapusi Srinivas PRASAD ,  Michael IGNATOWSKI ,  Niti MADAN

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2275

Abstract: A memory device includes memory cells. A memory cell of the memory cells includes gate circuitry, a first capacitor, and a second capacitor. The gate circuitry is connected to a wordline and a bitline. The first capacitor is connected to the gate circuitry and a first drive line. The second capacitor is connected to the gate circuitry and a second drive line.

公开(公告)号：US20240087631A1

公开(公告)日：2024-03-14

申请号：US18216499

申请日：2023-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Divya Madapusi Srinivas PRASAD ,  Michael IGNATOWSKI

IPC: G11C11/22 ,  G11C19/00

CPC classification number: G11C11/221 ,  G11C19/005

Abstract: A memory device includes a memory circuitry includes a first transmission grate, a first capacitor, a second transmission gate, and a second capacitor. The first transmission gate includes a first transistor connected between a first node and a second node. The first transistor having a gate terminal connected to a first clock node. The first clock node configured to receive a first clock signal. The first capacitor is connected between the second node and a first voltage node. The first capacitor is a ferroelectric capacitor. The second transmission gate includes a second transistor connected between the second node and a third node. The second transistor has a gate terminal connected to the first clock node. The second capacitor is connected between the third node and a second voltage node.