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公开(公告)号：US20240088099A1
公开(公告)日：2024-03-14
申请号：US18215681
申请日：2023-06-28
IPC分类号： H01L25/065 , G11C11/4097 , H01L25/18
CPC分类号： H01L25/0657 , G11C11/4097 , H01L25/18 , H01L2225/06555
摘要： Memory stacks having substantially vertical bitlines, and chip packages having the same, are disclosed herein. In one example, a memory stack is provided that includes a first memory IC die and a second memory IC die. The second memory IC die is stacked on the first memory IC die. Bitlines are routed through the first and second IC dies in a substantially vertical orientation. Wordlines within the first memory IC die are oriented orthogonal to the bitlines.
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公开(公告)号：US20240088098A1
公开(公告)日：2024-03-14
申请号：US18199837
申请日：2023-05-19
IPC分类号： H01L25/065 , H10B80/00
CPC分类号： H01L25/0657 , H10B80/00 , H01L2225/06503
摘要： Disclosed wherein stacked memory dies that utilize a mix of high and low operational temperature memory and non-volatile based memory dies, and chip packages containing the same. High temperature memory dies, such as those using non-volatile memory (NVM) technologies are in a memory stack with low temperature memory dies, such as those having volatile memory technologies. In some cases, the high temperature memory technologies could be used together, in some cases, on the same IC die as logic circuitry. In one example, a memory stack is provided that include a first memory IC die having high temperature memory circuitry, such as non-volatile memory, stacked below a second memory IC die. The second memory IC die has high temperature memory circuitry, such as volatile memory circuitry.
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公开(公告)号：US20180060257A1
公开(公告)日：2018-03-01
申请号：US15663403
申请日：2017-07-28
CPC分类号： G06F13/1673 , G06F11/1004 , G06F13/1689
摘要： A memory module includes a memory, a cache to cache copies of information stored in the memory, and a controller. The controller is configured to access first data from the memory or the cache in response to receiving a read request from a processor. The controller is also configured to transmit a first signal a first nondeterministic time interval after receiving the read request. The first signal indicates that the first data is available. The controller is further configured to transmit a second signal a first deterministic time interval after receiving a first transmit request from the processor in response to the first signal. The second signal includes the first data. The memory module also includes a buffer to store a write request until completion and a counter that is incremented in response to receiving the write request and decremented in response to completing the write request.
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公开(公告)号：US20150261662A1
公开(公告)日：2015-09-17
申请号：US14206512
申请日：2014-03-12
IPC分类号： G06F12/02
CPC分类号： G06F12/023 , G06F12/0284 , G06F2212/1044
摘要： A multilevel memory system includes a plurality of memories and a processor having a memory controller. The memory controller classifies each memory in accordance with a plurality of memory classes based on its level, its type, or both. The memory controller partitions a unified memory address space into contiguous address blocks and allocates the address blocks among the memory classes. In some implementations, the memory controller then can partition the address blocks assigned to each given memory class into address subblocks and interleave the address subblocks among the memories of the memory class.
摘要翻译： 多级存储器系统包括多个存储器和具有存储器控制器的处理器。 存储器控制器根据其级别，类型或两者根据多个存储器类别对每个存储器进行分类。 存储器控制器将统一的存储器地址空间划分成连续的地址块，并在存储器类之间分配地址块。 在一些实现中，存储器控制器然后可以将分配给每个给定存储器类的地址块划分为地址子块，并且交织存储器类的存储器中的地址子块。
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公开(公告)号：US20240087632A1
公开(公告)日：2024-03-14
申请号：US18216501
申请日：2023-06-29
IPC分类号： G11C11/22
CPC分类号： G11C11/2273 , G11C11/2255 , G11C11/2257 , G11C11/2275
摘要： A memory device includes memory cells. A memory cell of the memory cells includes gate circuitry, a first capacitor, and a second capacitor. The gate circuitry is connected to a wordline and a bitline. The first capacitor is connected to the gate circuitry and a first drive line. The second capacitor is connected to the gate circuitry and a second drive line.
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公开(公告)号：US20240087631A1
公开(公告)日：2024-03-14
申请号：US18216499
申请日：2023-06-29
CPC分类号： G11C11/221 , G11C19/005
摘要： A memory device includes a memory circuitry includes a first transmission grate, a first capacitor, a second transmission gate, and a second capacitor. The first transmission gate includes a first transistor connected between a first node and a second node. The first transistor having a gate terminal connected to a first clock node. The first clock node configured to receive a first clock signal. The first capacitor is connected between the second node and a first voltage node. The first capacitor is a ferroelectric capacitor. The second transmission gate includes a second transistor connected between the second node and a third node. The second transistor has a gate terminal connected to the first clock node. The second capacitor is connected between the third node and a second voltage node.
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7.发明申请公开(公告)号：US20140181457A1
公开(公告)日：2014-06-26
申请号：US13725305
申请日：2012-12-21
发明人： Lisa R. HSU , Gabriel H. LOH , Michael IGNATOWSKI , Michael J. SCHULTE , Nuwan S. JAYASENA , James M. O'CONNOR
IPC分类号： G06F12/10
CPC分类号： G06F12/10 , G06F11/1666 , G06F11/2094
摘要： A system, method, and memory device embodying some aspects of the present invention for remapping external memory addresses and internal memory locations in stacked memory are provided. The stacked memory includes one or more memory layers configured to store data. The stacked memory also includes a logic layer connected to the memory layer. The logic layer has an Input/Output (I/O) port configured to receive read and write commands from external devices, a memory map configured to maintain an association between external memory addresses and internal memory locations, and a controller coupled to the I/O port, memory map, and memory layers, configured to store data received from external devices to internal memory locations.
摘要翻译： 提供体现本发明的一些方面的用于重新映射外部存储器地址和堆叠存储器中的内部存储器位置的系统，方法和存储器件。 堆叠的存储器包括被配置为存储数据的一个或多个存储器层。 堆叠的存储器还包括连接到存储器层的逻辑层。 逻辑层具有被配置为从外部设备接收读取和写入命令的输入/输出（I / O）端口，被配置为保持外部存储器地址和内部存储器位置之间的关联的存储器映射以及耦合到I / O端口，内存映射和内存层，配置为将从外部设备接收的数据存储到内部存储器位置。
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