公开(公告)号：US12181955B1

公开(公告)日：2024-12-31

申请号：US18087894

申请日：2022-12-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Lu Lu ,  Dong Zhu ,  Gia Phan ,  James A. Ott ,  Nehal Patel ,  Zang SongGan

IPC: G06F11/07 ,  G06F11/34 ,  G06F11/36

Abstract: A computer-implemented method for enabling debugging can include receiving, at a peripheral device connected through an expansion socket to a base CPU platform, a scan dump instruction from a network computing device connected to the base CPU platform across a network connection and executing, by a System-on-Chip at the peripheral device in response to the scan dump instruction, a debugging procedure. The debugging procedure can include capturing a snapshot of memory of the peripheral device and transmitting the snapshot to the network computing device through memory addresses that have been assigned to memory-mapped input/output. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20250102570A1

公开(公告)日：2025-03-27

申请号：US18475047

申请日：2023-09-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Nehal Patel

IPC: G01R31/317 ,  G01R31/319

Abstract: A disclosed technique includes based on a clock pattern, determining an enable configuration for setting enable signals for one or more multi-cycle paths of a hardware logic network; controlling a selector to set the enable configuration for the one or more multi-cycle paths; and executing testing operations for the hardware logic network with the one or more multi-cycle paths enabled according to the enable configuration.

公开(公告)号：US20240168513A1

公开(公告)日：2024-05-23

申请号：US17990566

申请日：2022-11-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Nehal Patel

IPC: G06F1/10

CPC classification number: G06F1/10

Abstract: A disclosed technique includes clock gating a plurality of data elements of a first clock domain of a scan dump network; outputting data from a plurality of data elements of a second clock domain of the scan dump network; clock gating the plurality of data elements of the second clock domain; and outputting data from the plurality of data elements of the first clock domain.

公开(公告)号：US09377506B2

公开(公告)日：2016-06-28

申请号：US14230139

申请日：2014-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Shantanu Sarangi ,  Nehal Patel ,  Christian Warling

IPC: G01R31/28 ,  G01R31/317

CPC classification number: G01R31/31705

Abstract: A system, method, and tangible computer readable medium for chip debug is disclosed. For example, the system can include a plurality of functional blocks, a debug path, and a debug bus steering module. The debug path couples the plurality of functional blocks in a daisy chain configuration, where an end functional block from the plurality of functional blocks is at an end of the daisy chain configuration. The debug bus steering module is configured to pass one or more debug signals associated with a first functional block from the plurality of functional blocks along the debug path to the end functional block while a second functional block from the plurality of functional blocks performs one or more power gating cycles.

Abstract translation: 公开了一种用于芯片调试的系统，方法和有形计算机可读介质。 例如，该系统可以包括多个功能块，调试路径和调试总线转向模块。 调试路径以菊花链配置耦合多个功能块，其中来自多个功能块的端部功能块处于菊花链配置的结尾。 调试总线转向模块被配置为将来自多个功能块的与第一功能块相关联的一个或多个调试信号沿调试路径传递到终端功能块，而来自多个功能块的第二功能块执行一个或多个 电源门控周期。

公开(公告)号：US20150276868A1

公开(公告)日：2015-10-01

申请号：US14230139

申请日：2014-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Shantanu SARANGI ,  Nehal Patel ,  Christian Warling

IPC: G01R31/3177

CPC classification number: G01R31/31705

Abstract: A system, method, and tangible computer readable medium for chip debug is disclosed. For example, the system can include a plurality of functional blocks, a debug path, and a debug bus steering module. The debug path couples the plurality of functional blocks in a daisy chain configuration, where an end functional block from the plurality of functional blocks is at an end of the daisy chain configuration. The debug bus steering module is configured to pass one or more debug signals associated with a first functional block from the plurality of functional blocks along the debug path to the end functional block while a second functional block from the plurality of functional blocks performs one or more power gating cycles.

Abstract translation: 公开了一种用于芯片调试的系统，方法和有形计算机可读介质。 例如，该系统可以包括多个功能块，调试路径和调试总线转向模块。 调试路径以菊花链配置耦合多个功能块，其中来自多个功能块的端部功能块处于菊花链配置的结尾。 调试总线转向模块被配置为将来自多个功能块的与第一功能块相关联的一个或多个调试信号沿调试路径传递到终端功能块，而来自多个功能块的第二功能块执行一个或多个 电源门控周期。

公开(公告)号：US20250006290A1

公开(公告)日：2025-01-02

申请号：US18343377

申请日：2023-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Nehal Patel

IPC: G11C29/36 ,  G11C29/12 ,  G11C29/56

Abstract: Some implementations provide systems methods and devices for integrated circuit self-test. The integrated circuit includes interface circuitry configured to read test data and to write the test data into memory of the integrated circuit. The integrated circuit also includes test circuitry configured to test the interface circuitry based on the test data written into memory of the integrated circuit. Some implementations provide an integrated circuit configured for storing and reading data. The integrated circuit includes circuitry configured to write or read a first portion of data to or from a first memory via BIST circuitry of the first memory until a first BIST counter saturates. The integrated circuit also includes circuitry configured to write or read a second portion of the data to or from a second memory via BIST circuitry of the second memory until a second BIST counter saturates.

公开(公告)号：US12135577B2

公开(公告)日：2024-11-05

申请号：US17990566

申请日：2022-11-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Nehal Patel

IPC: G06F1/10

Abstract: A disclosed technique includes clock gating a plurality of data elements of a first clock domain of a scan dump network; outputting data from a plurality of data elements of a second clock domain of the scan dump network; clock gating the plurality of data elements of the second clock domain; and outputting data from the plurality of data elements of the first clock domain.