公开(公告)号：US20180240777A1

公开(公告)日：2018-08-23

申请号：US15956704

申请日：2018-04-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shih-Ming HUANG ,  Chun-Hung LIN ,  Yi-Ting CHEN ,  Wen-Hsin LIN ,  Shih-Wei CHAN ,  Yung-Hsing CHANG

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/295 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor process includes: applying an encapsulation material on an upper surface of a first substrate to encapsulate a die and first conductive parts, wherein the encapsulation material is a B-stage adhesive; forming a plurality of openings on the encapsulation material to expose the first conductive parts; pressing a second substrate onto the encapsulation material to adhere a lower surface of the second substrate to the encapsulation material, wherein the second substrate includes second conductive parts, and each of the first conductive parts contacts a corresponding one of the second conductive parts; and heating to fuse the first conductive parts and the corresponding second conductive parts to form a plurality of interconnection elements and solidify the encapsulation material to form a C-stage adhesive.

公开(公告)号：US20170110392A1

公开(公告)日：2017-04-20

申请号：US14884582

申请日：2015-10-15

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Chun-Hung LIN ,  Yi-Ting CHEN ,  Shih-Ming HUANG ,  Ching-Rong LIN

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/92225 ,  H01L2924/15331 ,  H01L2924/3511

Abstract: A semiconductor package structure includes a first semiconductor substrate, a second semiconductor substrate, a semiconductor die electrically connected to the first semiconductor substrate, an interconnection element and an encapsulant. The first semiconductor substrate includes a first top pad, and the second semiconductor substrate includes a second bottom pad. The interconnection element connects the second bottom pad and the first top pad. The interconnection element includes a first cupped portion and a second arcuate portion, where the first portion is connected to the first top pad and the second portion is connected to the second bottom pad. The first portion and the second portion together define the interconnection element as a monolithic component. The encapsulant is disposed between the first semiconductor substrate and the second semiconductor substrate, and covers the semiconductor die and the interconnection element.

公开(公告)号：US20140367841A1

公开(公告)日：2014-12-18

申请号：US14303421

申请日：2014-06-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shih-Ming HUANG ,  Chun-Hung LIN ,  Yi-Ting CHEN ,  Wen-Hsin LIN ,  Shih-Wei CHAN ,  Yung-Hsing CHANG

IPC: H01L23/053 ,  H01L23/00

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/295 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/0401

Abstract: The present disclosure relates to a semiconductor package structure and semiconductor process. The semiconductor package includes a first substrate, a second substrate, a die, a plurality of interconnection elements and an encapsulation material. Each of the interconnection elements connects the first substrate and the second substrate. The encapsulation material encapsulates the interconnection elements. The encapsulation material defines a plurality of accommodation spaces to accommodate the interconnection elements, and the profile of each accommodation space is defined by the individual interconnection element, whereby the warpage behavior of the first substrate is in compliance with that of the second substrate during reflow.

Abstract translation: 本公开涉及半导体封装结构和半导体工艺。 半导体封装包括第一衬底，第二衬底，裸片，多个互连元件和封装材料。 每个互连元件连接第一基板和第二基板。 封装材料封装互连元件。 封装材料限定多个容纳空间以容纳互连元件，并且每个容纳空间的轮廓由单独的互连元件限定，由此第一衬底的翘曲行为在回流期间与第二衬底的翘曲行为一致。