公开(公告)号：US11387213B2

公开(公告)日：2022-07-12

申请号：US16894630

申请日：2020-06-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shun Sing Liao

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: A method for manufacturing a semiconductor package includes: (a) providing a substrate structure, wherein the substrate structure includes a chip attach area, a bottom area opposite to the chip attach area, a lower side rail surrounding the bottom area, a first lower structure and a second lower structure, wherein the first lower structure is disposed in a first lower region of the lower side rail, and a second lower occupancy ratio is greater than a first lower occupancy ratio; (b) attaching at least one semiconductor chip to the chip attach area; and (c) forming an encapsulant to cover the at least one semiconductor chip.

公开(公告)号：US11367676B2

公开(公告)日：2022-06-21

申请号：US16569234

申请日：2019-09-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shun Sing Liao

IPC: H01L23/49 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31

Abstract: A semiconductor device package includes a substrate, a semiconductor device and an encapsulant. The substrate includes a passivation layer, a first conductive layer and a barrier layer. The passivation layer has a substantially vertical sidewall. The first conductive layer is disposed on the passivation layer. The barrier layer is disposed on the passivation layer and the first conductive layer. The barrier layer includes a substantially slant sidewall.

公开(公告)号：US11756926B2

公开(公告)日：2023-09-12

申请号：US17752796

申请日：2022-05-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shun Sing Liao

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/49838 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L23/49827 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/98 ,  H01L2924/3511

Abstract: A method for manufacturing a semiconductor package includes: (a) providing a substrate structure, wherein the substrate structure includes a chip attach area, a bottom area opposite to the chip attach area, a lower side rail surrounding the bottom area, a first lower structure and a second lower structure, wherein the first lower structure is disposed in a first lower region of the lower side rail, and a second lower occupancy ratio is greater than a first lower occupancy ratio; (b) attaching at least one semiconductor chip to the chip attach area; and (c) forming an encapsulant to cover the at least one semiconductor chip.

公开(公告)号：US11342304B2

公开(公告)日：2022-05-24

申请号：US16894630

申请日：2020-06-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shun Sing Liao

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: A method for manufacturing a semiconductor package includes: (a) providing a substrate structure, wherein the substrate structure includes a chip attach area, a bottom area opposite to the chip attach area, a lower side rail surrounding the bottom area, a first lower structure and a second lower structure, wherein the first lower structure is disposed in a first lower region of the lower side rail, and a second lower occupancy ratio is greater than a first lower occupancy ratio; (b) attaching at least one semiconductor chip to the chip attach area; and (c) forming an encapsulant to cover the at least one semiconductor chip.

公开(公告)号：US11114389B2

公开(公告)日：2021-09-07

申请号：US16573895

申请日：2019-09-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shun Sing Liao

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A substrate structure includes a chip attach area and an upper side rail surrounding the chip attach area. The upper side rail includes an upper stress relief structure and an upper reinforcing structure. The upper stress relief structure surrounds the upper chip attach area. The upper reinforcing structure surrounds the upper stress relief structure. A stress relieving ability of the upper stress relief structure is greater than a stress relieving ability of the upper reinforcing structure. A structural strength of the upper reinforcing structure is greater than a structural strength of the upper stress relief structure.