公开(公告)号：US20220384208A1

公开(公告)日：2022-12-01

申请号：US17332854

申请日：2021-05-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chia-Pin CHEN ,  Chia Sheng TIEN ,  Wan-Ting CHIU ,  Chi Long TSAI ,  Cyuan-Hong SHIH ,  Yen Liang CHEN

IPC: H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: A manufacturing method for manufacturing a package structure is provided. The manufacturing method includes: (a) providing a carrier having a top surface and a lateral side surface, wherein the top surface includes a main portion and a flat portion connecting the lateral side surface, and a first included angle between the main portion and the flat portion is less than a second included angle between the main portion and the lateral side surface; (b) forming an under layer on the carrier to at least partially expose the flat portion; and (c) forming a dielectric layer on the under layer and covering the exposed flat portion.

公开(公告)号：US20170040279A1

公开(公告)日：2017-02-09

申请号：US15297691

申请日：2016-10-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wan-Ting CHIU ,  Chien-Fan CHEN

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/562 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/022 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/1411 ,  H01L2224/17107 ,  H01L2225/06513 ,  H01L2924/07025 ,  H01L2924/35

Abstract: The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

Abstract translation: 本公开涉及在半导体封装中有用的结合结构。 在一个实施例中，半导体器件包括半导体元件，两个柱结构和绝缘层。 半导体元件具有表面并且包括邻近表面设置的至少一个焊盘。 两个柱结构设置在单个焊盘上。 绝缘层邻近半导体元件的表面设置。 绝缘层限定开口，开口暴露单个焊盘的一部分，并且两个柱结构设置在开口中。

公开(公告)号：US20160307864A1

公开(公告)日：2016-10-20

申请号：US14691448

申请日：2015-04-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wan-Ting CHIU ,  Chien-Fan CHEN

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/562 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/022 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/1411 ,  H01L2224/17107 ,  H01L2225/06513 ,  H01L2924/07025 ,  H01L2924/35

Abstract: The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element and two pillar structures. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on the one bonding pad. The two pillar structures are symmetric and formed of a same material

Abstract translation: 本公开涉及在半导体封装中有用的结合结构。 在一个实施例中，半导体器件包括半导体元件和两个支柱结构。 半导体元件具有表面并且包括邻近表面设置的至少一个焊盘。 两个支柱结构设置在一个焊盘上。 两个柱结构是对称的，由相同的材料形成

公开(公告)号：US20220367306A1

公开(公告)日：2022-11-17

申请号：US17317762

申请日：2021-05-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chia-Pin CHEN ,  Chia-Sheng TIEN ,  Wan-Ting CHIU ,  Chi Long TSAI

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L25/065

Abstract: An electronic device package includes an encapsulated electronic component, a substrate, a conductor and a buffer layer. The encapsulated electronic component includes a redistribution layer (RDL) and an encapsulation layer. The first surface is closer to the RDL than the second surface is. The encapsulation layer includes a first surface, and a second surface opposite to the first surface. The substrate is disposed on the second surface of the encapsulation layer. The conductor is disposed between the substrate and the encapsulated electronic component, and electrically connecting the substrate to the encapsulated electronic component. The buffer layer is disposed between the substrate and the encapsulated electronic component and around the conductor.