公开(公告)号：US20230164920A1

公开(公告)日：2023-05-25

申请号：US18095511

申请日：2023-01-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Fan CHEN ,  Chien-Hao WANG

IPC: H05K1/18 ,  H01L21/48 ,  H01L23/538 ,  H01L21/56

CPC classification number: H05K1/183 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L21/568 ,  H01L23/5386 ,  H05K2201/10 ,  H01L2924/15153 ,  H01L2224/04105 ,  H01L2924/11

Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.

公开(公告)号：US20220216136A1

公开(公告)日：2022-07-07

申请号：US17142198

申请日：2021-01-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Po-Jen CHENG ,  Chien-Fan CHEN

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56

Abstract: An electronic device package and a method for manufacturing the same are provided. The electronic device package includes a circuit layer and an electronic component. The circuit layer includes a dielectric layer having an opening, and an electrical contact. A width of an aperture of the opening increases from a first surface toward a second surface. The electrical contact is at least partially disposed in the opening and exposed through the opening. The electronic component is disposed on the second surface and electrically connected to the circuit layer.

公开(公告)号：US20210287997A1

公开(公告)日：2021-09-16

申请号：US16814704

申请日：2020-03-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Fan CHEN ,  Yu-Ju LIAO

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed.

公开(公告)号：US20200296836A1

公开(公告)日：2020-09-17

申请号：US16351026

申请日：2019-03-12

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Yu-Ju LIAO ,  Chien-Fan CHEN ,  Chien-Hao WANG ,  I-Chia LIN

IPC: H05K1/18 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

Abstract: An embedded component package structure including a circuit substrate, an embedded component and a stress compensation layer is provided. The circuit substrate includes a core layer and an asymmetric circuit structure, and the core layer has a first thickness. The embedded component is disposed in the core layer. The stress compensation layer is disposed on one side of the core layer, and the stress compensation layer has a second thickness between 4 μm and 351 μm.

公开(公告)号：US20220278052A1

公开(公告)日：2022-09-01

申请号：US17746790

申请日：2022-05-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Fan CHEN ,  Yu-Ju LIAO

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48

Abstract: The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed.

公开(公告)号：US20210280521A1

公开(公告)日：2021-09-09

申请号：US16813369

申请日：2020-03-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Fan CHEN ,  Yu-Ju LIAO ,  Chu-Jie YANG ,  Sheng-Hung SHIH

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48

Abstract: A substrate structure is disclosed. The substrate structure includes a carrier, a dielectric layer on the carrier, a patterned organic core layer in the dielectric layer, and a conductive via. The patterned organic core layer defines a passage extending in the dielectric layer towards the carrier. The conductive via extends through the passage towards the carrier without contacting the patterned organic core layer.

公开(公告)号：US20170040279A1

公开(公告)日：2017-02-09

申请号：US15297691

申请日：2016-10-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wan-Ting CHIU ,  Chien-Fan CHEN

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/562 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/022 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/1411 ,  H01L2224/17107 ,  H01L2225/06513 ,  H01L2924/07025 ,  H01L2924/35

Abstract: The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

Abstract translation: 本公开涉及在半导体封装中有用的结合结构。 在一个实施例中，半导体器件包括半导体元件，两个柱结构和绝缘层。 半导体元件具有表面并且包括邻近表面设置的至少一个焊盘。 两个柱结构设置在单个焊盘上。 绝缘层邻近半导体元件的表面设置。 绝缘层限定开口，开口暴露单个焊盘的一部分，并且两个柱结构设置在开口中。

公开(公告)号：US20210298176A1

公开(公告)日：2021-09-23

申请号：US17342363

申请日：2021-06-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Fan CHEN ,  Chien-Hao WANG

IPC: H05K1/18 ,  H01L21/48 ,  H01L23/538 ,  H01L21/56

Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.

公开(公告)号：US20160307864A1

公开(公告)日：2016-10-20

申请号：US14691448

申请日：2015-04-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wan-Ting CHIU ,  Chien-Fan CHEN

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/562 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/022 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/1411 ,  H01L2224/17107 ,  H01L2225/06513 ,  H01L2924/07025 ,  H01L2924/35

Abstract: The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element and two pillar structures. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on the one bonding pad. The two pillar structures are symmetric and formed of a same material

Abstract translation: 本公开涉及在半导体封装中有用的结合结构。 在一个实施例中，半导体器件包括半导体元件和两个支柱结构。 半导体元件具有表面并且包括邻近表面设置的至少一个焊盘。 两个支柱结构设置在一个焊盘上。 两个柱结构是对称的，由相同的材料形成

公开(公告)号：US20160211235A1

公开(公告)日：2016-07-21

申请号：US14599366

申请日：2015-01-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Dao-Long CHEN ,  Ping-Feng YANG ,  Chang-Chi LEE ,  Chien-Fan CHEN

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/0614 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13007 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1414 ,  H01L2224/16055 ,  H01L2224/16056 ,  H01L2224/81191 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar. The body includes a first surface. The at least one conductive metal pad is disposed on the first surface. Each metal pillar is formed on a corresponding conductive metal pad. Each metal pillar has a concave side wall and a convex side wall opposite the first concave side wall, and the concave side wall and the convex side wall are orthogonal to the corresponding conductive metal pad.

Abstract translation: 本公开涉及凸块结构以及具有该凸块结构的半导体器件和半导体器件封装。 半导体器件包括主体，至少一个导电金属焊盘和至少一个金属支柱。 身体包括第一表面。 至少一个导电金属垫设置在第一表面上。 每个金属柱形成在相应的导电金属垫上。 每个金属柱具有与第一凹入侧壁相对的凹侧壁和凸侧壁，并且凹侧壁和凸侧壁与相应的导电金属垫正交。