-
公开(公告)号:US20220005771A1
公开(公告)日:2022-01-06
申请号:US17480123
申请日:2021-09-20
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Wen Hung HUANG , Yan Wen CHUNG , Wei Chu SUN
IPC: H01L23/66 , H01L23/498 , H01L23/00
Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.
-
公开(公告)号:US20200279815A1
公开(公告)日:2020-09-03
申请号:US16289072
申请日:2019-02-28
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Wen Hung HUANG , Yan Wen CHUNG , Huei-Shyong CHO
IPC: H01L23/00 , H01L23/498 , H01L23/552 , H01L21/48 , H01L21/66 , H01L21/683 , H01L23/66
Abstract: A wiring structure includes a conductive structure, a surface structure and at least one through via. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The surface structure is disposed adjacent to a top surface of the conductive structure. The through via extends through the surface structure and extending into at least a portion of the conductive structure.
-
公开(公告)号:US20210159168A1
公开(公告)日:2021-05-27
申请号:US16696825
申请日:2019-11-26
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Wen Hung HUANG , Yan Wen CHUNG , Min Lung HUANG
IPC: H01L23/522 , H01L23/31 , H01L21/768 , H01L21/56 , H01L21/48 , H01L21/027 , H01L23/00
Abstract: A semiconductor package may include a first substrate and a second substrate, a redistribution layer (RDL), a first conductive via and a second conductive via. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a first surface and a second surface opposite to the first surface. The RDL is disposed on the first surface of the first substrate and the first surface of the second substrate. The first conductive via passes through the RDL and is electrically connected to the first substrate. The second conductive via passes through the RDL and is electrically connected to the second substrate.
-
公开(公告)号:US20180350616A1
公开(公告)日:2018-12-06
申请号:US15614563
申请日:2017-06-05
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Wen Hung HUANG , Yan Wen CHUNG , Chien-Mei HUANG
IPC: H01L21/3105 , H01L23/00 , H01L23/522 , H01L21/768 , H01L23/14 , H01L23/04 , G03F9/00
Abstract: A wiring structure includes a dielectric layer and a first patterned conductive layer on the dielectric layer. The dielectric layer has a first region and a second region. The first patterned conductive layer includes a number of fine conductive lines and a number of dummy conductive structures. The number of conductive lines include a first number of conductive lines on the first region and a second number of conductive lines on the second region, and the number of dummy conductive structures include a first number of dummy conductive structures on the second region. The first number of conductive lines occupy a first area on the first region, and the second number of conductive lines and the first number of dummy conductive structures occupy a second area on the second region. A ratio of the second area to the first area is greater than or equal to about 80%.
-
公开(公告)号:US20200381369A1
公开(公告)日:2020-12-03
申请号:US16996872
申请日:2020-08-18
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Wen Hung HUANG , Yan Wen CHUNG , Huei-Shyong CHO
IPC: H01L23/00 , H01L23/498 , H01L21/48 , H01L23/552 , H01L23/66 , H01L21/66 , H01L21/683
Abstract: A wiring structure includes a conductive structure, a surface structure and at least one through via. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The surface structure is disposed adjacent to a top surface of the conductive structure. The through via extends through the surface structure and extending into at least a portion of the conductive structure.
-
公开(公告)号:US20190221446A1
公开(公告)日:2019-07-18
申请号:US15870315
申请日:2018-01-12
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Wen Hung HUANG , Yan Wen CHUNG
IPC: H01L21/48 , H01L23/498 , H01L23/00 , H01L23/66
CPC classification number: H01L21/4857 , H01L21/481 , H01L21/4853 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/66 , H01L24/16 , H01L24/81 , H01L2223/6655 , H01L2224/16012 , H01L2224/16227 , H01L2224/16237 , H01L2224/81191 , H01L2224/81385 , H01L2224/81395 , H01L2224/81801
Abstract: A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.
-
公开(公告)号:US20180366402A1
公开(公告)日:2018-12-20
申请号:US15625920
申请日:2017-06-16
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Wen Hung HUANG , Yan Wen CHUNG , Wei Chu SUN
IPC: H01L23/498 , H01L23/00
Abstract: The present disclosure relates to a wiring structure and a semiconductor package. The wiring structure comprises a first wiring pattern, a dielectric layer and a dummy structure. The first wiring pattern includes a conductive land having a width W1 and a surface area A, and a conductive trace having a width W2 and electrically connected to the conductive land, wherein ((W1*W2)/A)*100% about 25%. The dielectric layer covers the first wiring pattern, and the dummy structure is adjacent to the conductive trace.
-
公开(公告)号:US20210013163A1
公开(公告)日:2021-01-14
申请号:US16508219
申请日:2019-07-10
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Wen Hung HUANG , Yan Wen CHUNG , Wei Chu SUN
IPC: H01L23/66 , H01L23/498 , H01L23/00
Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.
-
公开(公告)号:US20200273722A1
公开(公告)日:2020-08-27
申请号:US16870738
申请日:2020-05-08
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Wen Hung HUANG , Yan Wen CHUNG
IPC: H01L21/48 , H01L23/498 , H01L23/66 , H01L21/683 , H01L21/56
Abstract: A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.
-
公开(公告)号:US20200211945A1
公开(公告)日:2020-07-02
申请号:US16236207
申请日:2018-12-28
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Wen Hung HUANG , Li-Yu HSIEH , Yan Wen CHUNG
IPC: H01L23/498 , H01L21/48 , H01L21/66 , H01L21/683 , H01L23/544
Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an adhesion layer and at least one outer via. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The adhesion layer is interposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The outer via extends through at least a portion of the upper conductive structure and the adhesion layer, and electrically connected to the circuit layer of the lower conductive structure
-
-
-
-
-
-
-
-
-