公开(公告)号：US20220278052A1

公开(公告)日：2022-09-01

申请号：US17746790

申请日：2022-05-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Fan CHEN ,  Yu-Ju LIAO

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48

Abstract: The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed.

公开(公告)号：US20210280521A1

公开(公告)日：2021-09-09

申请号：US16813369

申请日：2020-03-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Fan CHEN ,  Yu-Ju LIAO ,  Chu-Jie YANG ,  Sheng-Hung SHIH

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48

Abstract: A substrate structure is disclosed. The substrate structure includes a carrier, a dielectric layer on the carrier, a patterned organic core layer in the dielectric layer, and a conductive via. The patterned organic core layer defines a passage extending in the dielectric layer towards the carrier. The conductive via extends through the passage towards the carrier without contacting the patterned organic core layer.

公开(公告)号：US20220165683A1

公开(公告)日：2022-05-26

申请号：US17105277

申请日：2020-11-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung HUANG ,  Yu-Ju LIAO

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56

Abstract: An assembly structure and a method for manufacturing the same are provided. The method for manufacturing the assembly structure includes providing a substrate defining an active region and a side rail surrounding the active region; and forming a frame structure on the side rail.

公开(公告)号：US20210287997A1

公开(公告)日：2021-09-16

申请号：US16814704

申请日：2020-03-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Fan CHEN ,  Yu-Ju LIAO

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed.

公开(公告)号：US20200296836A1

公开(公告)日：2020-09-17

申请号：US16351026

申请日：2019-03-12

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Yu-Ju LIAO ,  Chien-Fan CHEN ,  Chien-Hao WANG ,  I-Chia LIN

IPC: H05K1/18 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

Abstract: An embedded component package structure including a circuit substrate, an embedded component and a stress compensation layer is provided. The circuit substrate includes a core layer and an asymmetric circuit structure, and the core layer has a first thickness. The embedded component is disposed in the core layer. The stress compensation layer is disposed on one side of the core layer, and the stress compensation layer has a second thickness between 4 μm and 351 μm.

公开(公告)号：US20210074554A1

公开(公告)日：2021-03-11

申请号：US16565064

申请日：2019-09-09

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Chien-Fan CHEN ,  Yu-Ju LIAO

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: An embedded component package structure including a dielectric structure, a semiconductor chip and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure, and the dielectric structure encapsulates the semiconductor chip and has a first thickness. The semiconductor chip having a second thickness, and the first thickness is greater than the second thickness, and a ratio of the first thickness to the second thickness is between 1.1 and 28.4. The patterned conductive layer covers an upper surface of the dielectric structure and extending into a first opening of the dielectric structure. The first opening exposes an electrical pad of the semiconductor chip, and the patterned conductive layer is electrically connected to the electrical pad of the semiconductor chip.

公开(公告)号：US20200343188A1

公开(公告)日：2020-10-29

申请号：US16397539

申请日：2019-04-29

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Yu-Ju LIAO ,  Chien-Fan CHEN ,  Chien-Hao WANG

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/67 ,  H05K3/46

Abstract: An embedded component package structure including a dielectric structure and a component is provided. The component is embedded in the dielectric structure and is provided with a plurality of conductive pillars. The conductive pillars are exposed from an upper surface of the dielectric structure and have a first thickness and a second thickness, respectively, and the first thickness is not equal to the second thickness.

公开(公告)号：US20200343187A1

公开(公告)日：2020-10-29

申请号：US16397530

申请日：2019-04-29

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Yu-Ju LIAO ,  Chien-Fan CHEN ,  Chien-Hao WANG

IPC: H01L23/538 ,  H01L21/48 ,  H05K3/46

Abstract: An embedded component package structure including a dielectric structure, a semiconductor chip, a first polymer layer, and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure. The first polymer layer covers the semiconductor chip and has a first thickness, and the first thickness is greater than a second thickness of the dielectric structure above the first polymer layer. The patterned conductive layer covers an upper surface of the dielectric structure and extends over the first polymer layer, and the patterned conductive layer is electrically connected to the semiconductor chip.