公开(公告)号：US5923977A

公开(公告)日：1999-07-13

申请号：US970347

申请日：1997-11-14

申请人： Aftab Ahmad ,  David J. Keller ,  Tyler A. Lowrey

发明人： Aftab Ahmad ,  David J. Keller ,  Tyler A. Lowrey

IPC分类号： H01L21/8234 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/10873 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/1052 ,  H01L27/10894

摘要： A method for forming CMOS DRAM circuitry is disclosed and which includes forming a substrate comprising an array NMOS region, a peripheral NMOS region, and a peripheral PMOS region; forming a pair of insulated and spaced gate lines in the array NMOS region; forming at least one electrically conductive plug in the array NMOS region and which spans between the pair of gate lines; forming a barrier layer over the pair of gate lines in the array NMOS region, the peripheral NMOS and the peripheral PMOS region; and patterning and etching in the peripheral PMOS region to form peripheral PMOS region gate lines including removing a portion of the barrier layer in the PMOS peripheral region and leaving barrier layer material in the NMOS region masking over the electrically conductive plug.

摘要翻译： 公开了一种用于形成CMOS DRAM电路的方法，其包括形成包括阵列NMOS区，外围NMOS区和外围PMOS区的衬底; 在阵列NMOS区域中形成一对绝缘和间隔开的栅极线; 在所述阵列NMOS区域中形成至少一个导电插塞，并跨越所述一对栅极线; 在阵列NMOS区域，外围NMOS和外围PMOS区域中的一对栅极线上形成阻挡层; 以及在外围PMOS区域中图案化和蚀刻以形成外围PMOS区栅极线，包括去除PMOS外围区域中的一部分势垒层，并且使NMOS区域中的阻挡层材料掩蔽在导电插塞上。

公开(公告)号：US6136637A

公开(公告)日：2000-10-24

申请号：US124560

申请日：1998-07-28

申请人： Aftab Ahmad ,  David J. Keller ,  Tyler A. Lowrey

发明人： Aftab Ahmad ,  David J. Keller ,  Tyler A. Lowrey

IPC分类号： H01L21/8234 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8238

CPC分类号： H01L27/10873 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/1052 ,  H01L27/10894

摘要： A method for forming CMOS DRAM circuitry is disclosed and which includes forming a substrate comprising an array NMOS region, a peripheral NMOS region, and a peripheral PMOS region; forming a pair of insulated and spaced gate lines in the array NMOS region; forming at least one electrically conductive plug in the array NMOS region and which spans between the pair of gate lines; forming a barrier layer over the pair of gate lines in the array NMOS region, the peripheral NMOS and the peripheral PMOS region; and patterning and etching in the peripheral PMOS region to form peripheral PMOS region gate lines including removing a portion of the barrier layer in the PMOS peripheral region and leaving barrier layer material in the NMOS region masking over the electrically conductive plug

摘要翻译： 公开了一种用于形成CMOS DRAM电路的方法，其包括形成包括阵列NMOS区，外围NMOS区和外围PMOS区的衬底; 在阵列NMOS区域中形成一对绝缘和间隔开的栅极线; 在所述阵列NMOS区域中形成至少一个导电插塞，并跨越所述一对栅极线; 在阵列NMOS区域，外围NMOS和外围PMOS区域中的一对栅极线上形成阻挡层; 并且在外围PMOS区域中图案化和蚀刻以形成外围PMOS区域栅极线，包括去除PMOS外围区域中的一部分势垒层，并且使阻挡层材料留在导电插塞

公开(公告)号：US5811329A

公开(公告)日：1998-09-22

申请号：US655683

申请日：1996-06-03

申请人： Aftab Ahmad ,  David J. Keller ,  Tyler A. Lowrey

发明人： Aftab Ahmad ,  David J. Keller ,  Tyler A. Lowrey

IPC分类号： H01L21/8234 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8238

CPC分类号： H01L27/10873 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/1052 ,  H01L27/10894

摘要： A method for forming CMOS DRAM circuitry is disclosed and which includes forming a substrate comprising an array NMOS region, a peripheral NMOS region, and a peripheral PMOS region; forming a pair of insulated and spaced gate lines in the array NMOS region; forming at least one electrically conductive plug in the array NMOS region and which spans between the pair of gate lines; forming a barrier layer over the pair of gate lines in the array NMOS region, the peripheral NMOS and the peripheral PMOS region; and patterning and etching in the peripheral PMOS region to form peripheral PMOS region gate lines including removing a portion of the barrier layer in the PMOS peripheral region and leaving barrier layer material in the NMOS region masking over the electrically conductive plug.

公开(公告)号：US5405791A

公开(公告)日：1995-04-11

申请号：US317280

申请日：1994-10-04

申请人： Aftab Ahmad ,  Tyler A. Lowrey

发明人： Aftab Ahmad ,  Tyler A. Lowrey

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823864

摘要： This invention is a process for fabricating ultra-large-scale integration CMOS circuits using a single polysilicon gate layer for both N-channel and P-channel devices, a single mask step for defining the gates of both N-channel and P-channel devices, the fabrication of one set of disposable spacers for N-channel implants, and the fabrication of another set of disposable spacers for P-channel source/drain implants. The set of spacers used for P-channel implants also comprises material deposited to fabricate the spacers for the N-channel implants. The process is adaptable to LDD structures for both N-channel and P-channel devices or for only N-channel devices. The process is also compatible with anti-punchthrough implants for both types of devices.

摘要翻译： 本发明是用于制造用于N沟道和P沟道器件的单个多晶硅栅极层的超大规模集成CMOS电路的方法，用于定义N沟道和P沟道器件的栅极的单个掩模步骤 ，制造一组用于N沟道植入物的一次性间隔件，以及制造另一组用于P沟道源/漏植入物的一次性隔离物。 用于P沟道植入物的一组间隔物还包括沉积以制造用于N沟道植入物的间隔物的材料。 该过程适用于N沟道和P沟道器件的LDD结构，或仅适用于N沟道器件。 该过程也兼容两种类型设备的抗穿透植入物。

公开(公告)号：US06552394B2

公开(公告)日：2003-04-22

申请号：US09998420

申请日：2001-11-29

申请人： Aftab Ahmad ,  David J. Keller

发明人： Aftab Ahmad ,  David J. Keller

IPC分类号： H01L2976

CPC分类号： H01L29/6653 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6659 ,  H01L29/7833

摘要： The invention encompasses a transistor device comprising a region of a semiconductor material, and a transistor gate over a portion of the region. The device comprises a pair of opposing sidewall spacers adjacent sidewalls of the transistor gate and a pair of opposing first conductivity type source/drain regions within the semiconductor material proximate the transistor gate. The entirety of the semiconductor material under one of the sidewall spacers being defined as a first segment, and the entirety of the semiconductor material which is under the other of the sidewall spacers being defined as a second segment. The first and second segments of the semiconductor material are separated from the first and second source/drain regions by first and second gap regions, respectively, of the semiconductor material. The device further comprises a pair of opposing second conductivity type halo regions within the first and second gap regions.

摘要翻译： 本发明包括一种包括半导体材料的区域的晶体管器件以及该区域的一部分上的晶体管栅极。 该器件包括邻近晶体管栅极的一对相对的侧壁间隔件和邻近晶体管栅极的半导体材料内的一对相对的第一导电类型源/漏区。 在一个侧壁间隔物之下的半导体材料的整体被定义为第一段，并且位于另一个侧壁间隔物之下的半导体材料的整体被定义为第二段。 半导体材料的第一和第二段分别由半导体材料的第一和第二间隙区域与第一和第二源极/漏极区分离。 该装置还包括在第一和第二间隙区域内的一对相对的第二导电类型的晕圈区域。

公开(公告)号：US06319779B1

公开(公告)日：2001-11-20

申请号：US09167175

申请日：1998-10-06

申请人： Aftab Ahmad ,  David J. Keller

发明人： Aftab Ahmad ,  David J. Keller

IPC分类号： H01L218234

CPC分类号： H01L29/6653 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6659 ,  H01L29/7833

摘要： The invention includes a method for forming graded junction regions comprising: a) providing a semiconductor material wafer; b) providing a transistor gate over the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) providing sidewall spacers adjacent the sidewalls of the transistor gate, the sidewall spacers having a lateral thickness; d) decreasing the lateral thickness of the sidewall spacers; and e) after decreasing the lateral thickness of the sidewall spacers, implanting a conductivity-enhancing dopant into the semiconductor material to form graded junction regions operatively adjacent the transistor gate. The invention also includes a semiconductor transistor device comprising: a) a region of a semiconductor material wafer; b) a transistor gate over a portion of the region of the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) opposing source/drain regions operatively adjacent the transistor gate, each source/drain region having an inner lateral boundary; d) opposing sidewall spacers adjacent the sidewalls of the transistor gate, each sidewall spacer having an outer lateral edge, the sidewall spacers and source/drain regions being paired such that the outer lateral edges of the sidewall spacers are displaced laterally inwardly relative to the inner lateral boundaries of the source/drain regions; and e) lateral gaps, the lateral gaps extending from the outer lateral edges of the sidewall spacers to the inner lateral boundaries of the source/drain regions.

摘要翻译： 本发明包括一种用于形成渐变连接区域的方法，包括：a）提供半导体材料晶片; b）在所述半导体材料晶片上提供晶体管栅极，所述晶体管栅极具有相对的侧向侧壁; c）提供与所述晶体管栅极的侧壁相邻的侧壁间隔件，所述侧壁间隔件具有横向厚度; d）减小侧壁间隔物的横向厚度; 以及e）在减小所述侧壁间隔物的横向厚度之后，将导电性增强掺杂剂注入到所述半导体材料中以形成与所述晶体管栅极可操作地相邻的渐变连接区域。 本发明还包括半导体晶体管器件，其包括：a）半导体材料晶片的区域; b）在所述半导体材料晶片的所述区域的一部分上的晶体管栅极，所述晶体管栅极具有相对的侧向侧壁; c）与所述晶体管栅极可操作地相邻的源极/漏极区域，每个源极/漏极区域具有内侧边界; d）与晶体管栅极的侧壁相邻的相对的侧壁间隔件，每个侧壁间隔件具有外侧边缘，所述侧壁间隔件和源极/漏极区域成对，使得侧壁间隔件的外侧边缘相对于内侧 源极/漏极区域的横向边界; 以及e）横向间隙，所述侧向间隙从侧壁间隔件的外侧边缘延伸到源极/漏极区域的内侧边界。

公开(公告)号：US6165827A

公开(公告)日：2000-12-26

申请号：US167312

申请日：1998-10-06

申请人： Aftab Ahmad ,  David J. Keller

发明人： Aftab Ahmad ,  David J. Keller

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/6653 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6659 ,  H01L29/7833

摘要： The invention includes a method for forming graded junction regions comprising: a) providing a semiconductor material wafer; b) providing a transistor gate over the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) providing sidewall spacers adjacent the sidewalls of the transistor gate, the sidewall spacers having a lateral thickness; d) decreasing the lateral thickness of the sidewall spacers; and e) after decreasing the lateral thickness of the sidewall spacers, implanting a conductivity-enhancing dopant into the semiconductor material to form graded junction regions operatively adjacent the transistor gate. The invention also includes a semiconductor transistor device comprising: a) a region of a semiconductor material wafer; b) a transistor gate over a portion of the region of the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) opposing source/drain regions operatively adjacent the transistor gate, each source/drain region having an inner lateral boundary; d) opposing sidewall spacers adjacent the sidewalls of the transistor gate, each sidewall spacer having an outer lateral edge, the sidewall spacers and source/drain regions being paired such that the outer lateral edges of the sidewall spacers are displaced laterally inwardly relative to the inner lateral boundaries of the source/drain regions; and e) lateral gaps, the lateral gaps extending from the outer lateral edges of the sidewall spacers to the inner lateral boundaries of the source/drain regions.

公开(公告)号：US06346439B1

公开(公告)日：2002-02-12

申请号：US08677266

申请日：1996-07-09

申请人： Aftab Ahmad ,  David J. Keller

发明人： Aftab Ahmad ,  David J. Keller

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6659 ,  H01L29/7833

摘要： The invention includes a method for forming graded junction regions comprising: a) providing a semiconductor material wafer; b) providing a transistor gate over the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) providing sidewall spacers adjacent the sidewalls of the transistor gate, the sidewall spacers having a lateral thickness; d) decreasing the lateral thickness of the sidewall spacers; and e) after decreasing the lateral thickness of the sidewall spacers, implanting a conductivity-enhancing dopant into the semiconductor material to form graded junction regions operatively adjacent the transistor gate. The invention also includes a semiconductor transistor device comprising: a) a region of a semiconductor material wafer; b) a transistor gate over a portion of the region of the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) opposing source/drain regions operatively adjacent the transistor gate, each source/drain region having an inner lateral boundary; d) opposing sidewall spacers adjacent the sidewalls of the transistor gate, each sidewall spacer having an outer lateral edge, the sidewall spacers and source/drain regions being paired such that the outer lateral edges of the sidewall spacers are displaced laterally inwardly relative to the inner lateral boundaries of the source/drain regions; and e) lateral gaps, the lateral gaps extending from the outer lateral edges of the sidewall spacers to the inner lateral boundaries of the source/drain regions.

摘要翻译： 本发明包括一种用于形成渐变连接区域的方法，包括：a）提供半导体材料晶片; b）在所述半导体材料晶片上提供晶体管栅极，所述晶体管栅极具有相对的侧向侧壁; c）提供与所述晶体管栅极的侧壁相邻的侧壁间隔件，所述侧壁间隔件具有横向厚度; d）减小侧壁间隔物的横向厚度; 以及e）在减小所述侧壁间隔物的横向厚度之后，将导电性增强掺杂剂注入到所述半导体材料中以形成与所述晶体管栅极可操作地相邻的渐变连接区域。 本发明还包括半导体晶体管器件，其包括：a）半导体材料晶片的区域; b）在所述半导体材料晶片的所述区域的一部分上的晶体管栅极，所述晶体管栅极具有相对的侧向侧壁; c）与所述晶体管栅极可操作地相邻的源极/漏极区域，每个源极/漏极区域具有内侧边界; d）与晶体管栅极的侧壁相邻的相对的侧壁间隔件，每个侧壁间隔件具有外侧边缘，所述侧壁间隔件和源极/漏极区域成对，使得侧壁间隔件的外侧边缘相对于内侧 源极/漏极区域的横向边界; 以及e）横向间隙，所述侧向间隙从所述侧壁间隔物的外侧边缘延伸到所述源极/漏极区域的内侧边界。

公开(公告)号：US06333539B1

公开(公告)日：2001-12-25

申请号：US09167174

申请日：1998-10-06

申请人： Aftab Ahmad ,  David J. Keller

发明人： Aftab Ahmad ,  David J. Keller

IPC分类号： H01L2976

CPC分类号： H01L29/6653 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6659 ,  H01L29/7833

摘要： In one aspect, the invention encompasses a transistor device comprising a region of a semiconductor material wafer, and a transistor gate over a portion of the region. The transistor gate has a pair of opposing sidewalls which are a first sidewall and a second sidewall. The device further comprises a pair of opposing sidewall spacers adjacent the sidewalls of the transistor gate and a pair of opposing first conductivity type source/drain regions within the semiconductor material wafer proximate the transistor gate. One of the sidewall spacers extends along the first sidewall of the gate and the other of the sidewall spacers extends along the second sidewall of the gate. The entirety of the semiconductor wafer material under one of the sidewall spacers being defined as a first segment of the semiconductor wafer material, and the entirety of the semiconductor wafer material which is under the other of the sidewall spacers being defined as a second segment of the semiconductor wafer material. The first and second segments of the semiconductor material wafer are separated from the first and second source/drain regions by first and second gap regions, respectively, of the semiconductor material wafer. The device further comprises a pair of opposing second conductivity type halo regions within the first and second gap regions.

摘要翻译： 在一个方面，本发明包括一种晶体管器件，其包括半导体材料晶片的区域和该区域的一部分上的晶体管栅极。 晶体管栅极具有一对相对的侧壁，它们是第一侧壁和第二侧壁。 该器件还包括邻近晶体管栅极的侧壁的一对相对的侧壁间隔物和靠近晶体管栅极的半导体材料晶片内的一对相对的第一导电类型源极/漏极区域。 侧壁间隔件中的一个沿着栅极的第一侧壁延伸，并且另一个侧壁间隔件沿着栅极的第二侧壁延伸。 将侧壁间隔物之一的半导体晶片材料的整体定义为半导体晶片材料的第一段，并且位于另一侧壁间隔物之下的整个半导体晶片材料被定义为第二段 半导体晶片材料。 半导体材料晶片的第一和第二段分别由半导体材料晶片的第一和第二间隙区域与第一和第二源极/漏极区分离。 该装置还包括在第一和第二间隙区域内的一对相对的第二导电类型的晕圈区域。

公开(公告)号：US07176549B2

公开(公告)日：2007-02-13

申请号：US11012012

申请日：2004-12-13

申请人： Klaus F. Schuegraf ,  Aftab Ahmad

发明人： Klaus F. Schuegraf ,  Aftab Ahmad

IPC分类号： H01L29/00

CPC分类号： H01L21/76224 ,  Y10S148/05

摘要： A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.

摘要翻译： 公开了一种浅沟槽隔离，其中沟槽深度减小到超过现有技术工艺中所达到的深度。 减小的沟槽深度有助于在沟槽再填充过程期间消除空隙的形成，并且在最终隔离结构中提供更大的平坦度。 通过利用具有低介电常数的再填充介电材料，通过减小沟槽深度实现有效的器件隔离。