公开(公告)号：US08367303B2

公开(公告)日：2013-02-05

申请号：US11487246

申请日：2006-07-14

申请人： David J. Keller ,  Alex Schrinsky

发明人： David J. Keller ,  Alex Schrinsky

IPC分类号： G03F7/26

CPC分类号： H01L21/31122 ,  G03F1/00 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

摘要： The critical dimension (CD) of features formed during the fabrication of a semiconductor device may be controlled through the use of a dry develop chemistry comprising O2, SO2 and a hydrogen halide. For example, a dry develop chemistry comprising a gas comprising O2 and a gas comprising SO2 and a gas comprising HBr may be used to remove exposed areas of a carbon-based mask. The addition of HBr to the conventional O2 and SO2 dry develop chemistry enables a user to tune the critical dimension by growing, trimming and/or sloping the sidewalls and to enhance sidewall passivation and reduce sidewall bowing.

摘要翻译： 在制造半导体器件期间形成的特征的临界尺寸（CD）可以通过使用包含O 2，SO 2和卤化氢的干式显影化学品来控制。 例如，包括包含O 2的气体和包含SO 2的气体和包含HBr的气体的干式显影化学物质可用于除去碳基掩模的暴露区域。 向传统的O2和SO2干式开发化学物质中添加HBr可使用户通过增长，修整和/或倾斜侧壁来调节临界尺寸，并增强侧壁钝化并减少侧壁弯曲。

公开(公告)号：US20090209072A1

公开(公告)日：2009-08-20

申请号：US12031015

申请日：2008-02-14

申请人： David J. Keller

发明人： David J. Keller

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L27/10873 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/28255 ,  H01L29/42368

摘要： Some embodiments include methods of forming transistor gates. A gate stack is placed within a reaction chamber and subjected to at least two etches, and to one or more depositions to form a transistor gate. The transistor gate may comprise at least one electrically conductive layer over a semiconductor material-containing layer. At least one of the one or more depositions may form protective material. The protective material may extend entirely across the at least one electrically conductive layer, and only partially across the semiconductor material-containing layer to leave unlined portions of the semiconductor material-containing layer. The unlined portions of the semiconductor material-containing layer may be subsequently oxidized.

摘要翻译： 一些实施例包括形成晶体管栅极的方法。 将栅极堆叠放置在反应室内并经历至少两个蚀刻，并进行一个或多个沉积以形成晶体管栅极。 晶体管栅极可以包括含半导体材料的层上的至少一个导电层。 一个或多个沉积中的至少一个可以形成保护材料。 保护材料可以完全延伸穿过至少一个导电层，并且仅部分地横跨含半导体材料的层，以留下含半导体材料的层的无衬里部分。 半导体材料含有层的无衬里部分可随后被氧化。

公开(公告)号：US5652170A

公开(公告)日：1997-07-29

申请号：US589622

申请日：1996-01-22

申请人： David J. Keller ,  Louie Liu ,  Kris K. Brown

发明人： David J. Keller ,  Louie Liu ,  Kris K. Brown

IPC分类号： H01L21/02 ,  H01L21/3213 ,  H01L21/8242 ,  H01L21/70

CPC分类号： H01L28/90 ,  H01L21/32137 ,  H01L27/10852 ,  Y10S148/014 ,  Y10S438/978

摘要： Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle with of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier. The etch is subsequently performed with the use of a diatomic chlorine etchant. Four embodiments are disclosed as variations on the step of etching the polysilicon with the diatomic chlorine etch chemistry.

摘要翻译： 公开了一种垂直取向的电容器结构，其在MOS DRAM存储器模块中是特别有用的。 该结构具有由介电层隔开的上下多晶硅电容器板，每个板和电介质层相对于下面的硅衬底以大约80-85度的角度倾斜。 因此，新颖的电容器形成在倾斜的接触开口中。 下部电容器板与下面的有源区域的电连接的接触区域具有足够小的水平横截面，使得接触区域不会横向延伸超过有源区域，并且不会发生泄漏。 公开了一种用于形成接触开口的方法，首先，形成有源区，优选地位于两个绝缘鸟的喙区之间，并用薄层的氧化物蚀刻阻挡材料覆盖有源区。 然后在氧化物蚀刻阻挡层上方形成多晶硅层。 随后使用双原子氯蚀刻剂进行蚀刻。 作为对使用双原子氯蚀刻化学品蚀刻多晶硅的步骤的变化，公开了四个实施例。

公开(公告)号：US5492597A

公开(公告)日：1996-02-20

申请号：US242230

申请日：1994-05-13

申请人： David J. Keller

发明人： David J. Keller

IPC分类号： C23C16/44 ,  C23F1/12 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/00

CPC分类号： H01L21/02071 ,  C23C16/4405 ,  C23F1/12 ,  H01L21/32135 ,  H01L21/32137

摘要： The present invention teaches a method for etching a tungsten silicide (WSi.sub.x) film overlying a polysilicon film in an enclosed chamber during a semiconductor fabrication process, by the steps of: providing a patterned mask overlying the WSi.sub.x film thereby providing exposed portions of the WSi.sub.x film; presenting an etchant chemistry comprising NF.sub.3 and HeO.sub.2 to the exposed portions of the WSi.sub.x film at a temperature ranging from -20.degree. C. to 100.degree. C., thereby etching away the exposed portions of the WSi.sub.x film and simultaneously etching substantially vertical sidewalls in the WSi.sub.x film, the etching continues into the polysilicon film, thereby forming a WSi.sub.x /polysilicon stack having substantially vertical sidewalls.

摘要翻译： 本发明教导了一种用于在半导体制造工艺期间蚀刻覆盖封闭室中的多晶硅膜的硅化钨（WSix）膜的方法，其步骤为：提供覆盖在WSix膜上的图案掩模，从而提供WSix膜的暴露部分 ; 在-20℃至100℃的温度范围内向WSix膜的暴露部分提供包含NF 3和HeO 2的蚀刻剂化学品，从而蚀刻除去WSix膜的暴露部分，同时蚀刻WSix膜中的基本上垂直的侧壁 WSix膜，蚀刻继续进入多晶硅膜，从而形成具有基本垂直侧壁的WSix /多晶硅堆叠。

公开(公告)号：US5338395A

公开(公告)日：1994-08-16

申请号：US29262

申请日：1993-03-10

申请人： David J. Keller ,  Debra K. Gould

发明人： David J. Keller ,  Debra K. Gould

IPC分类号： H01L21/311 ,  H01L21/306

CPC分类号： H01L21/31116

摘要： An etch process wherein halogen ions are employed to bombard a patterned nitride layer thereby creating substantially vertical sidewalls, especially useful when etching submicron features.A process in which NF.sub.3 ions are combined with halogen ions in a reactive ion etcher to etch a patterned layer, followed, in situ, by an overetch of NF.sub.3 ions and an ionized hydrogen halide. An inert gas can be added to further increase the uniformity of the etch.

摘要翻译： 一种蚀刻工艺，其中使用卤素离子来轰击图案化的氮化物层，从而产生基本上垂直的侧壁，在蚀刻亚微米特征时特别有用。 其中NF 3离子与反应离子蚀刻剂中的卤素离子结合以蚀刻图案层，然后在原位通过NF 3离子和电离卤化氢的过蚀刻的过程。 可以加入惰性气体以进一步提高蚀刻的均匀性。

公开(公告)号：US5256245A

公开(公告)日：1993-10-26

申请号：US928922

申请日：1992-08-11

申请人： David J. Keller ,  Guy T. Blalock

发明人： David J. Keller ,  Guy T. Blalock

IPC分类号： H01L21/3213 ,  H01L21/306 ,  B44C1/22

CPC分类号： H01L21/32137 ,  Y10S438/905

摘要： Disclosed is a process step performed during a wafer etch which allows for the formation of more vertical sidewalls. During a conventional etch step of a material such as oxide, oxygen is released into the etch chamber, which is known to adversely affect the vertical profile of the sidewalls. The oxygen is known to combine with silicon and HBr, which are present as gasses within the etch chamber during the subsequent poly etch, to deposit on the poly sidewalls. For this reason subsequent etches are conventionally performed in a separate etch chamber.The disclosed step introduces an oxygen-scavenging gas into the etch chamber prior to the subsequent etch of the polycrystalline silicon. The oxygen-scavenging gas combines with the liberated oxygen with the application of plasma energy to produce an inert volatile gas which can be pumped from the etch chamber and therefore not adversely affect subsequent etches. Claimed oxygen-scavenging gasses include C.sub.2 F.sub.6, CF.sub.4, CHF.sub.3, and BCl.sub.3.

摘要翻译： 公开了在晶片蚀刻期间执行的工艺步骤，其允许形成更垂直的侧壁。 在诸如氧化物的材料的常规蚀刻步骤期间，氧被释放到蚀刻室中，这已知会不利地影响侧壁的垂直轮廓。 已知氧与硅和HBr组合，其在随后的多晶硅蚀刻期间作为气体存在于蚀刻室内以沉积在聚侧壁上。 因此，以往的蚀刻通常在单独的蚀刻室中进行。 所公开的步骤在随后蚀刻多晶硅之前将氧气清除气体引入蚀刻室。 氧气清除气体与释放的氧气结合使用等离子体能量以产生惰性挥发性气体，其可从蚀刻室泵送，因此不会不利地影响随后的蚀刻。 声称的除氧气体包括C2F6，CF4，CHF3和BCl3。

公开(公告)号：US08043911B2

公开(公告)日：2011-10-25

申请号：US11972098

申请日：2008-01-10

申请人： David J. Keller

发明人： David J. Keller

IPC分类号： H01L21/8242

CPC分类号： H01L21/32136 ,  H01L21/32137 ,  H01L21/823842 ,  H01L21/823864

摘要： The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and partially into a silicon-containing layer beneath the titanium-containing layer. The etch can utilize CH2F2. The silicon-containing layer can contain an n-type doped region and a p-type doped region. In some methods, the silicon-containing layer can contain an n-type doped region laterally adjacent a p-type doped region, and the processing can be utilized to form a transistor gate containing n-type doped silicon simultaneously with the formation of a transistor gate containing p-type doped silicon.

摘要翻译： 本发明包括形成半导体结构的方法，其中使用单个蚀刻来穿透含钛层并部分地进入含钛层下面的含硅层。 蚀刻可以利用CH2F2。 含硅层可以包含n型掺杂区域和p型掺杂区域。 在一些方法中，含硅层可以包含横向邻近p型掺杂区域的n型掺杂区域，并且该处理可用于形成包含n型掺杂硅的晶体管栅极，同时形成晶体管 栅极包含p型掺杂硅。

公开(公告)号：US06346439B1

公开(公告)日：2002-02-12

申请号：US08677266

申请日：1996-07-09

申请人： Aftab Ahmad ,  David J. Keller

发明人： Aftab Ahmad ,  David J. Keller

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6659 ,  H01L29/7833

摘要： The invention includes a method for forming graded junction regions comprising: a) providing a semiconductor material wafer; b) providing a transistor gate over the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) providing sidewall spacers adjacent the sidewalls of the transistor gate, the sidewall spacers having a lateral thickness; d) decreasing the lateral thickness of the sidewall spacers; and e) after decreasing the lateral thickness of the sidewall spacers, implanting a conductivity-enhancing dopant into the semiconductor material to form graded junction regions operatively adjacent the transistor gate. The invention also includes a semiconductor transistor device comprising: a) a region of a semiconductor material wafer; b) a transistor gate over a portion of the region of the semiconductor material wafer, the transistor gate having opposing lateral sidewalls; c) opposing source/drain regions operatively adjacent the transistor gate, each source/drain region having an inner lateral boundary; d) opposing sidewall spacers adjacent the sidewalls of the transistor gate, each sidewall spacer having an outer lateral edge, the sidewall spacers and source/drain regions being paired such that the outer lateral edges of the sidewall spacers are displaced laterally inwardly relative to the inner lateral boundaries of the source/drain regions; and e) lateral gaps, the lateral gaps extending from the outer lateral edges of the sidewall spacers to the inner lateral boundaries of the source/drain regions.

摘要翻译： 本发明包括一种用于形成渐变连接区域的方法，包括：a）提供半导体材料晶片; b）在所述半导体材料晶片上提供晶体管栅极，所述晶体管栅极具有相对的侧向侧壁; c）提供与所述晶体管栅极的侧壁相邻的侧壁间隔件，所述侧壁间隔件具有横向厚度; d）减小侧壁间隔物的横向厚度; 以及e）在减小所述侧壁间隔物的横向厚度之后，将导电性增强掺杂剂注入到所述半导体材料中以形成与所述晶体管栅极可操作地相邻的渐变连接区域。 本发明还包括半导体晶体管器件，其包括：a）半导体材料晶片的区域; b）在所述半导体材料晶片的所述区域的一部分上的晶体管栅极，所述晶体管栅极具有相对的侧向侧壁; c）与所述晶体管栅极可操作地相邻的源极/漏极区域，每个源极/漏极区域具有内侧边界; d）与晶体管栅极的侧壁相邻的相对的侧壁间隔件，每个侧壁间隔件具有外侧边缘，所述侧壁间隔件和源极/漏极区域成对，使得侧壁间隔件的外侧边缘相对于内侧 源极/漏极区域的横向边界; 以及e）横向间隙，所述侧向间隙从所述侧壁间隔物的外侧边缘延伸到所述源极/漏极区域的内侧边界。

公开(公告)号：US6136637A

公开(公告)日：2000-10-24

申请号：US124560

申请日：1998-07-28

申请人： Aftab Ahmad ,  David J. Keller ,  Tyler A. Lowrey

发明人： Aftab Ahmad ,  David J. Keller ,  Tyler A. Lowrey

IPC分类号： H01L21/8234 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8238

CPC分类号： H01L27/10873 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/1052 ,  H01L27/10894

摘要： A method for forming CMOS DRAM circuitry is disclosed and which includes forming a substrate comprising an array NMOS region, a peripheral NMOS region, and a peripheral PMOS region; forming a pair of insulated and spaced gate lines in the array NMOS region; forming at least one electrically conductive plug in the array NMOS region and which spans between the pair of gate lines; forming a barrier layer over the pair of gate lines in the array NMOS region, the peripheral NMOS and the peripheral PMOS region; and patterning and etching in the peripheral PMOS region to form peripheral PMOS region gate lines including removing a portion of the barrier layer in the PMOS peripheral region and leaving barrier layer material in the NMOS region masking over the electrically conductive plug

摘要翻译： 公开了一种用于形成CMOS DRAM电路的方法，其包括形成包括阵列NMOS区，外围NMOS区和外围PMOS区的衬底; 在阵列NMOS区域中形成一对绝缘和间隔开的栅极线; 在所述阵列NMOS区域中形成至少一个导电插塞，并跨越所述一对栅极线; 在阵列NMOS区域，外围NMOS和外围PMOS区域中的一对栅极线上形成阻挡层; 并且在外围PMOS区域中图案化和蚀刻以形成外围PMOS区域栅极线，包括去除PMOS外围区域中的一部分势垒层，并且使阻挡层材料留在导电插塞

公开(公告)号：US5811329A

公开(公告)日：1998-09-22

申请号：US655683

申请日：1996-06-03

申请人： Aftab Ahmad ,  David J. Keller ,  Tyler A. Lowrey

发明人： Aftab Ahmad ,  David J. Keller ,  Tyler A. Lowrey

IPC分类号： H01L21/8234 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8238

CPC分类号： H01L27/10873 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/1052 ,  H01L27/10894

摘要： A method for forming CMOS DRAM circuitry is disclosed and which includes forming a substrate comprising an array NMOS region, a peripheral NMOS region, and a peripheral PMOS region; forming a pair of insulated and spaced gate lines in the array NMOS region; forming at least one electrically conductive plug in the array NMOS region and which spans between the pair of gate lines; forming a barrier layer over the pair of gate lines in the array NMOS region, the peripheral NMOS and the peripheral PMOS region; and patterning and etching in the peripheral PMOS region to form peripheral PMOS region gate lines including removing a portion of the barrier layer in the PMOS peripheral region and leaving barrier layer material in the NMOS region masking over the electrically conductive plug.