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    Timing recovery system
    3.
    发明授权
    Timing recovery system 失效
    定时恢复系统

    公开(公告)号：US6134276A

    公开(公告)日：2000-10-17

    申请号：US52454

    申请日：1998-03-31

    申请人： Ahmad K. Aman ,  Cecil William Farrow ,  Hong Jiang ,  Agesino Primatic, Jr. ,  Charles Albert Webb, III

    发明人： Ahmad K. Aman ,  Cecil William Farrow ,  Hong Jiang ,  Agesino Primatic, Jr. ,  Charles Albert Webb, III

    IPC分类号： H03J7/04 ,  H03L7/091 ,  H04L7/033 ,  H04L7/04 ,  H04L27/00 ,  H04L27/06 ,  H04L27/14

    CPC分类号： H04L7/046 ,  H03J7/04 ,  H03L7/091 ,  H04L27/066 ,  H04L7/0334 ,  H04L7/042 ,  H04L2027/0067 ,  H04L2027/0073 ,  H04L2027/0081

    摘要： A digital timing recovery system advantageously employs both demodulated I-phase and Q-phase components to more accurately locate the synchronization signal of an incoming VSB signal. The Q-phase component is advantageously employed to detect the phase error. The use of the Q-phase component provides a more accurate measure of the phase error and results in a larger (wider) acquisition range for timing frequency offset. More specifically, the timing recovery system of this invention performs symbol clock recovery based on the VSB signal segment synchronization (sync) signal and generates a pulse density modulated (PDM) phase difference signal that controls a voltage controlled crystal oscillator (VCXO) in the phase-locked loop. This is realized, in one embodiment of the invention, by correlating received sync segment data with the known sync signal pattern and searching for "peaks" in the correlation values that are periodic at the known sync segment data rate. Once the sync pattern is found, the correlation values for adjacent samples are advantageously employed to generate the necessary feedback control signal value for the VCXO. Technical advantages of applicants' unique invention are that the need for an analog synchronous detector is eliminated, a more accurate measure than that obtained by prior known systems is obtained and a wider acquisition range is obtained for timing frequency offset.

    摘要翻译： 数字定时恢复系统有利地采用解调的I相和Q相分量来更准确地定位输入的VSB信号的同步信号。 Q相分量有利地用于检测相位误差。 使用Q相分量可以更准确地测量相位误差，并导致定时频率偏移的较大（较宽）采集范围。 更具体地，本发明的定时恢复系统基于VSB信号段同步（sync）信号执行符号时钟恢复，并生成在相位上控制压控晶体振荡器（VCXO）的脉冲密度调制（PDM）相位差信号 锁定环。 在本发明的一个实施例中，通过将接收到的同步段数据与已知的同步信号模式相关并在以已知的同步段数据速率周期性的相关值中搜索“峰值”来实现。 一旦找到同步模式，有利地采用相邻采样的相关值来为VCXO生成必要的反馈控制信号值。 申请人独特发明的技术优点是消除了对模拟同步检测器的需要，获得了比现有已知系统获得的更准确的测量值，并且获得了定时频率偏移的更宽的采集范围。

    Carrier recovery system
    4.
    发明授权
    Carrier recovery system 失效

    公开(公告)号：US06192088B1

    公开(公告)日：2001-02-20

    申请号：US09052455

    申请日：1998-03-31

    申请人： Ahmad K. Aman ,  Cecil William Farrow ,  Hong Jiang ,  Agesino Primatic, Jr. ,  Charles Albert Webb, III

    发明人： Ahmad K. Aman ,  Cecil William Farrow ,  Hong Jiang ,  Agesino Primatic, Jr. ,  Charles Albert Webb, III

    IPC分类号： H04L2714

    CPC分类号： H04L27/066 ,  H04L2027/0053 ,  H04L2027/0081 ,  H04L2027/0087

    摘要： A digital carrier recovery system includes at least two modes of operation, namely, an acquisition mode and a tracking mode. The bandwidth of the carrier recovery loop filter is different for the acquisition mode and the tracking mode. In the acquisition mode, the digital phase-locked loop seeks and locks to the long term frequency offset of the received carrier signal. In the tracking mode, the digital phase-locked loop tracks the instantaneous variations in the carrier phase. Switching between the acquisition mode and the tracking mode is realized digitally, and includes programmable hysteresis, resulting in optimal performance in the presence of signals having high levels of phase noise (jitter). More specifically, the carrier recovery loop filter “locks” to the pilot signal of an incoming signal, e.g., a vestigial side band (VSB) video signal, by employing a so-called digital vector tracking phase-locked loop that demodulates the VSB signal. The digital vector tracking phase-locked loop includes a complex filter, i.e., a so-called vector tracking filter, that very quickly locks to the pilot signal of the passband VSB signal and once locked to the pilot signal, switches to the tracking mode that provides significantly better tracking of phase noise. The demodulation is achieved by employing a complex multiplication of the incoming signal with a complex exponential sequence to obtain an in-phase (I-phase) component and a quadrature-phase (Q-phase) component. The complex exponential sequence is generated, in one embodiment, by employing a SIN/COS look up table that is driven by a phase difference signal generated by the digital vector tracking phase-locked loop. A residual direct current (dc) component in the I-phase component caused by the pilot signal is removed, resulting in a baseband I/Q signal. A technical advantage of this carrier recovery invention is that the bandwidth of the phase-locked loop filter can be different for the acquisition mode and the tracking mode. This allows for optimal performance in both the acquisition and tracking modes of operation.

    Addressing scheme for convolutional interleaver/de-interleaver
    5.
    发明授权
    Addressing scheme for convolutional interleaver/de-interleaver 失效
    卷积交织器/解交织器的寻址方案

    公开(公告)号：US06178530B1

    公开(公告)日：2001-01-23

    申请号：US09065854

    申请日：1998-04-24

    申请人： Ahmad K. Aman ,  Hermann J. Weckenbrock

    发明人： Ahmad K. Aman ,  Hermann J. Weckenbrock

    IPC分类号： G11C2900

    CPC分类号： H04L1/0071 ,  H03M13/2732 ,  H03M13/2764 ,  H04L1/0043 ,  H04L1/0052

    摘要： A memory addressing scheme suitable for use for either interleaving or de-interleaving data bytes of, e.g., a broadcast digital television (DTV) data stream. A number of memory branches are configured in a random access memory (RAM), wherein at least some of the branches have different numbers of memory locations for reading out and for storing data bytes, thus defining memory branches of different lengths in the RAM. A start address is determined for each of the memory branches in the RAM, corresponding to a first memory location of each branch. An offset value is determined for each memory branch, to be added to the start address for the branch for addressing a memory location of the branch. If an offset value does not exceed the length of a corresponding branch, an address corresponding to the sum of the branch start address and the offset value is generated for addressing a successive memory location of the branch, and the offset value for the branch is incremented by one. When an offset value equals the length of a corresponding branch, an address corresponding to a last memory location of the branch is generated, and the offset value for the branch is reset to zero.

    摘要翻译： 一种适用于交织或解交织例如广播数字电视（DTV）数据流的数据字节的存储器寻址方案。 多个存储器分支被配置在随机存取存储器（RAM）中，其中至少一些分支具有不同数量的存储器位置，用于读出和存储数据字节，从而定义RAM中不同长度的存储器分支。 确定对应于每个分支的第一存储器位置的RAM中的每个存储器分支的起始地址。 为每个存储器分支确定偏移值，以将其添加到用于寻址分支的存储器位置的分支的起始地址。 如果偏移值不超过相应分支的长度，则生成与分支起始地址和偏移值之和相对应的地址，用于寻址分支的连续存储位置，并且分支的偏移值增加 一个 当偏移值等于相应分支的长度时，生成与分支的最后一个存储单元对应的地址，并将分支的偏移值重置为零。