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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07092305B2

    公开(公告)日：2006-08-15

    申请号：US10822717

    申请日：2004-04-13

    申请人： Naoya Watanabe ,  Aiko Nishino ,  Katsumi Dosaka

    发明人： Naoya Watanabe ,  Aiko Nishino ,  Katsumi Dosaka

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C8/12 ,  G11C11/406 ,  G11C11/4085

    摘要： A main control circuit generates a plurality of main control signals of different phases to local control circuits. The local control circuits produce row-related control signals greater in number than the main control signals in accordance with these main control signals. A semiconductor memory device can be easily adapted to change in bank structure, and can perform a fast and stable operation with a low current consumption.

    摘要翻译： 主控制电路产生与本地控制电路不同相位的多个主控制信号。 根据这些主控制信号，本地控制电路产生数量大于主控制信号的行相关控制信号。 半导体存储器件可以容易地适应银行结构的改变，并且可以以低电流消耗来执行快速和稳定的操作。

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06888776B2

    公开(公告)日：2005-05-03

    申请号：US10077833

    申请日：2002-02-20

    申请人： Naoya Watanabe ,  Aiko Nishino ,  Katsumi Dosaka

    发明人： Naoya Watanabe ,  Aiko Nishino ,  Katsumi Dosaka

    IPC分类号： G11C8/12 ,  G11C11/406 ,  G11C11/408 ,  G11C8/00

    CPC分类号： G11C8/12 ,  G11C11/406 ,  G11C11/4085

    摘要： A main control circuit generates a plurality of main control signals of different phases to local control circuits. The local control circuits produce row-related control signals greater in number than the main control signals in accordance with these main control signals. A semiconductor memory device can be easily adapted to change in bank structure, and can perform a fast and stable operation with a low current consumption.

    摘要翻译： 主控制电路产生与本地控制电路不同相位的多个主控制信号。 根据这些主控制信号，本地控制电路产生数量大于主控制信号的行相关控制信号。 半导体存储器件可以容易地适应银行结构的改变，并且可以以低电流消耗来执行快速和稳定的操作。

    Synchronous semiconductor memory device with multi-bank configuration
    5.
    发明授权
    Synchronous semiconductor memory device with multi-bank configuration 失效
    具有多组配置的同步半导体存储器件

    公开(公告)号：US6091659A

    公开(公告)日：2000-07-18

    申请号：US318433

    申请日：1999-05-25

    申请人： Naoya Watanabe ,  Katsumi Dosaka

    发明人： Naoya Watanabe ,  Katsumi Dosaka

    IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/16 ,  G11C11/401 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C8/16 ,  G11C7/1006

    摘要： Memory blocks provided to share a sense amplifier band, a global IO (GIOB) bus provided in common to the memory blocks for transferring internal data, and local IO bus lines provided corresponding to the memory blocks are connection-controlled based on signals related to a column select operation. Driving memory blocks independently from each other permits each memory block to be used as a bank, and if one memory block is accessed during activation of another memory block, data can be prevented from colliding on the global IO bus. A main memory with high page hit rate is implemented using a semiconductor memory device with a shared-sense amplifier configuration. When a memory block sharing a sense amplifier coupled to another memory block is addressed, the another memory block is inactivated and then addressed memory block is accessed, when a valid data is output, such valid data outputting is signaled by a data valid signal.

    摘要翻译： 提供用于共享读出放大器频带的存储器块，共同提供用于传送内部数据的存储器块的全局IO（GIOB）总线以及与存储器块相对应地提供的本地IO总线的连接控制是基于与 列选择操作。 彼此独立地驱动存储器块允许每个存储器块用作存储体，并且如果在激活另一个存储器块期间访问一个存储器块，则可以防止数据在全局IO总线上冲突。 具有高页命中率的主存储器使用具有共享读出放大器配置的半导体存储器件来实现。 当共享耦合到另一个存储器块的读出放大器的存储器块被寻址时，另一个存储块被去激活，然后寻址存储器块被访问，当输出有效数据时，这样的有效数据输出由数据有效信号发出。

    Synchronous semiconductor memory device with multi-bank configuration
    8.
    发明授权
    Synchronous semiconductor memory device with multi-bank configuration 失效
    具有多组配置的同步半导体存储器件

    公开(公告)号：US5956285A

    公开(公告)日：1999-09-21

    申请号：US798953

    申请日：1997-02-11

    申请人： Naoya Watanabe ,  Katsumi Dosaka

    发明人： Naoya Watanabe ,  Katsumi Dosaka

    IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/16 ,  G11C11/401 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C8/16 ,  G11C7/1006

    摘要： Memory blocks provided to share a sense amplifier bank, a global IO (GIOB) bus provided in common to the memory blocks for transferring internal data, and local IO bus lines provided corresponding to the memory blocks are connected-controlled based on signals related to a column select operation. Driving memory blocks independently from each other permits each memory block to be used as a bank, and if one memory block is accessed during activation of another memory block, data can be prevented from colliding on the global IO bus. A main memory with high page hit rate is implemented using a semiconductor memory device with a shared-sense amplifier configuration. When a memory block sharing a sense amplifier coupled to another memory block is addressed, the another memory block is inactivated and then addressed memory block is accessed, when a valid data is output, such valid data outputting is signaled by a data valid signal.

    摘要翻译： 提供用于共享读出放大器组的存储器块，与用于传送内部数据的存储器块共同提供的全局IO（GIOB）总线，以及与存储块对应地提供的本地IO总线，基于与 列选择操作。 彼此独立地驱动存储器块允许每个存储器块用作存储体，并且如果在激活另一个存储器块期间访问一个存储器块，则可以防止数据在全局IO总线上冲突。 具有高页命中率的主存储器使用具有共享读出放大器配置的半导体存储器件来实现。 当共享耦合到另一个存储器块的读出放大器的存储器块被寻址时，另一个存储块被去激活，然后寻址存储器块被访问，当输出有效数据时，这样的有效数据输出由数据有效信号发出。

    Synchronous semiconductor memory device with multi-bank configuration
    10.
    发明授权
    Synchronous semiconductor memory device with multi-bank configuration 失效
    具有多组配置的同步半导体存储器件

    公开(公告)号：US06378102B1

    公开(公告)日：2002-04-23

    申请号：US09553957

    申请日：2000-04-21

    申请人： Naoya Watanabe ,  Katsumi Dosaka

    发明人： Naoya Watanabe ,  Katsumi Dosaka

    IPC分类号： G11C2900

    CPC分类号： G11C8/16 ,  G11C7/1006

    摘要： Memory blocks provided to share a sense amplifier band, a global IO (GIOB) bus provided in common to the memory blocks for transferring internal data, and local IO bus lines provided corresponding to the memory blocks are connection-controlled based on signals related to a column select operation. Driving memory blocks independently from each other permits each memory block to be used as a bank, and if one memory block is accessed during activation of another memory block, data can be prevented from colliding on the global IO bus. A main memory with high page hit rate is implemented using a semiconductor memory device with a shared-sense amplifier configuration. When a first memory block sharing a sense amplifier coupled to a second memory block is addressed, the second memory block is inactivated, and then the addressed first memory block is accessed, when a valid data is output, such valid data outputting is signaled by a data valid signal.

    摘要翻译： 提供用于共享读出放大器频带的存储器块，共同提供用于传送内部数据的存储器块的全局IO（GIOB）总线以及与存储器块相对应地提供的本地IO总线的连接控制是基于与 列选择操作。 彼此独立地驱动存储器块允许每个存储器块用作存储体，并且如果在激活另一个存储器块期间访问一个存储器块，则可以防止数据在全局IO总线上冲突。 具有高页命中率的主存储器使用具有共享读出放大器配置的半导体存储器件来实现。 当共享耦合到第二存储器块的读出放大器的第一存储器块被寻址时，第二存储器块被去激活，然后被寻址的第一存储器块被访问，当输出有效数据时，这样的有效数据输出由 数据有效信号。