公开(公告)号：US5257234A

公开(公告)日：1993-10-26

申请号：US842887

申请日：1992-02-26

申请人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

发明人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

IPC分类号： G11C8/00 ,  G11C8/10 ,  G11C13/00

CPC分类号： G11C8/10 ,  G11C8/00

摘要： Means for changing-over address signals is provided in an address input portion, and the order of the signals to be input to an address decoder is changed according to external control signals. Alternatively, a reading output circuit is provided which reads data in bit unit different from that of the writing input circuit. Thus, data can be read and written even when the number of bits of data differs between in case of accessing a built-in memory of an LSI inside the LSI and in case of accessing it from outside the LSI.

摘要翻译： 在地址输入部分提供用于切换地址信号的装置，并且根据外部控制信号改变要输入到地址解码器的信号的顺序。 或者，提供读取输出电路，其读取与写入输入电路不同的位单元的数据。 因此，即使在访问LSI内的LSI的内置存储器和从LSI外部访问的情况下，即使数据的位数不同，也可以读取和写入数据。

公开(公告)号：US5335204A

公开(公告)日：1994-08-02

申请号：US69988

申请日：1993-05-28

申请人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

发明人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

IPC分类号： G11C8/00 ,  G11C8/10 ,  G11C13/00

CPC分类号： G11C8/10 ,  G11C8/00

摘要： Means for changing-over address signals is provided in an address input portion, and the order of the signals to be input to an address decoder is changed according to external control signals. Alternatively, a reading output circuit is provided which reads data in bit unit different from that of the writing input circuit. Thus, data can be read and written even when the number of bits of data differs between in case of accessing a built-in memory of an LSI inside the LSI and in case of accessing it from outside the LSI.

摘要翻译： 在地址输入部分提供用于切换地址信号的装置，并且根据外部控制信号改变要输入到地址解码器的信号的顺序。 或者，提供读取输出电路，其读取与写入输入电路不同的位单元的数据。 因此，即使在访问LSI内的LSI的内置存储器和从LSI外部访问的情况下，即使数据的位数不同，也可以读取和写入数据。

公开(公告)号：US4989185A

公开(公告)日：1991-01-29

申请号：US219736

申请日：1988-07-15

申请人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

发明人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

IPC分类号： G11C8/00 ,  G11C8/10

CPC分类号： G11C8/10 ,  G11C8/00

摘要： A memory area within a semiconductor integrated circuit device is accessible through an address changeover circuit. External control signals instruct the memory device as to the addressing mode desired. Address signals originating externally are provided directly to the IC's address decoder circuits, while addresses originating internal to the IC are first shifted one or two bits to modify the address by a power of 2, then provided to the address decoder circuits. In this way, data of bit length N may be written to a memory array of bit length M, where M>N.

公开(公告)号：US5105389A

公开(公告)日：1992-04-14

申请号：US621643

申请日：1990-12-04

申请人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

发明人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

IPC分类号： G11C8/00 ,  G11C8/10

CPC分类号： G11C8/10 ,  G11C8/00

摘要： Means for changing-over address signals is provided in an address input portion, and the order of the signals to be input to an address decoder is changed according to external control signals. Alternatively, a reading output circuit is provided which reads data in bit unit different from that of the writing input circuit. Thus, data can be read and written even when the number of bits of data differs between in case of accessing a built-in memory of an LSI inside the LSI and in case of accessing it from outside the LSI.

公开(公告)号：US4596129A

公开(公告)日：1986-06-24

申请号：US544997

申请日：1983-10-24

申请人： Ryomyo Hamanaka ,  Michio Fujimoto

发明人： Ryomyo Hamanaka ,  Michio Fujimoto

IPC分类号： B21D31/04 ,  B21D53/02 ,  F28F1/12 ,  B21D53/04

CPC分类号： F28F1/122 ,  B21D31/046 ,  B21D53/02 ,  F28F1/128 ,  F28F2255/12

摘要： An apparatus, for forming fins for heat exchangers, comprising a pair of rolls which are provided, on the outer peripheral surfaces thereof, with grooves of a pattern corresponding to the shape of the fins to be formed therebetween and which form them by pressing the fins from opposite sides thereof with the aid of the synchronous rotation of the rolls to give smooth curved outer surfaces thereon, characterized in that the grooves on the rolls are formed so that each groove may be composed of a bottom portion having a substantially arcuate shape and a tapered portion converging from the outer peripheral surface toward the bottom portion of the roll as viewed in section, and at least one roll of the pair of rolls is provided with an urging means for pressing the aforesaid roll against the other roll at a constant pressure. An apparatus for forming needle fins for heat exchangers characterized by providing a means for alternately oppositely bending the fins which have been formed to be possessed of the curved outer surfaces. An apparatus for forming needle fins for heat exchangers characterized by further successively providing an arrangement forming roll area on a downstream side of the fin section forming roll area.

摘要翻译： 一种用于形成用于热交换器的翅片的装置，包括一对辊，其在其外周表面上设置有与要形成在其间的翅片的形状对应的图案的凹槽，并且通过按压翅片 借助于辊的同步旋转，在其上形成平滑弯曲的外表面，其特征在于，辊上的槽形成为使得每个槽可以由具有基本上弓形的底部和 从所述辊的外周面朝向所述底部部分收敛的锥形部分，并且所述一对辊的至少一个辊设置有用于以恒定压力将所述辊压在另一个辊上的施力装置。 一种用于形成用于热交换器的针状翅片的装置，其特征在于提供一种用于交替地相对地弯曲已经形成为具有弯曲外表面的翅片的装置。 一种用于形成用于热交换器的针翅片的装置，其特征在于，还进一步提供在所述翅片部分形成辊区域的下游侧上形成辊区域的布置。