公开(公告)号：US4989185A

公开(公告)日：1991-01-29

申请号：US219736

申请日：1988-07-15

申请人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

发明人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

IPC分类号： G11C8/00 ,  G11C8/10

CPC分类号： G11C8/10 ,  G11C8/00

摘要： A memory area within a semiconductor integrated circuit device is accessible through an address changeover circuit. External control signals instruct the memory device as to the addressing mode desired. Address signals originating externally are provided directly to the IC's address decoder circuits, while addresses originating internal to the IC are first shifted one or two bits to modify the address by a power of 2, then provided to the address decoder circuits. In this way, data of bit length N may be written to a memory array of bit length M, where M>N.

公开(公告)号：US5257234A

公开(公告)日：1993-10-26

申请号：US842887

申请日：1992-02-26

申请人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

发明人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

IPC分类号： G11C8/00 ,  G11C8/10 ,  G11C13/00

CPC分类号： G11C8/10 ,  G11C8/00

摘要： Means for changing-over address signals is provided in an address input portion, and the order of the signals to be input to an address decoder is changed according to external control signals. Alternatively, a reading output circuit is provided which reads data in bit unit different from that of the writing input circuit. Thus, data can be read and written even when the number of bits of data differs between in case of accessing a built-in memory of an LSI inside the LSI and in case of accessing it from outside the LSI.

摘要翻译： 在地址输入部分提供用于切换地址信号的装置，并且根据外部控制信号改变要输入到地址解码器的信号的顺序。 或者，提供读取输出电路，其读取与写入输入电路不同的位单元的数据。 因此，即使在访问LSI内的LSI的内置存储器和从LSI外部访问的情况下，即使数据的位数不同，也可以读取和写入数据。

公开(公告)号：US5105389A

公开(公告)日：1992-04-14

申请号：US621643

申请日：1990-12-04

申请人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

发明人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

IPC分类号： G11C8/00 ,  G11C8/10

CPC分类号： G11C8/10 ,  G11C8/00

摘要： Means for changing-over address signals is provided in an address input portion, and the order of the signals to be input to an address decoder is changed according to external control signals. Alternatively, a reading output circuit is provided which reads data in bit unit different from that of the writing input circuit. Thus, data can be read and written even when the number of bits of data differs between in case of accessing a built-in memory of an LSI inside the LSI and in case of accessing it from outside the LSI.

公开(公告)号：US5335204A

公开(公告)日：1994-08-02

申请号：US69988

申请日：1993-05-28

申请人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

发明人： Akinori Matsuo ,  Masashi Watanabe ,  Michio Fujimoto ,  Masashi Wada ,  Yoshiharu Nagayama ,  Kazuo Naito

IPC分类号： G11C8/00 ,  G11C8/10 ,  G11C13/00

CPC分类号： G11C8/10 ,  G11C8/00

摘要： Means for changing-over address signals is provided in an address input portion, and the order of the signals to be input to an address decoder is changed according to external control signals. Alternatively, a reading output circuit is provided which reads data in bit unit different from that of the writing input circuit. Thus, data can be read and written even when the number of bits of data differs between in case of accessing a built-in memory of an LSI inside the LSI and in case of accessing it from outside the LSI.

摘要翻译： 在地址输入部分提供用于切换地址信号的装置，并且根据外部控制信号改变要输入到地址解码器的信号的顺序。 或者，提供读取输出电路，其读取与写入输入电路不同的位单元的数据。 因此，即使在访问LSI内的LSI的内置存储器和从LSI外部访问的情况下，即使数据的位数不同，也可以读取和写入数据。

公开(公告)号：US4967387A

公开(公告)日：1990-10-30

申请号：US199605

申请日：1988-05-27

申请人： Nobuo Shibasaki ,  Toshio Tanaka ,  Yoshiharu Nagayama ,  Kenjiro Yasunari

发明人： Nobuo Shibasaki ,  Toshio Tanaka ,  Yoshiharu Nagayama ,  Kenjiro Yasunari

IPC分类号： G06F11/267 ,  G06F15/78 ,  G11C29/12 ,  G11C29/48

CPC分类号： G06F11/2236 ,  G06F15/7842 ,  G11C29/12 ,  G11C29/48

摘要： A microprocessor having a plurality of memories comprises an address selection means which supplies selectively, to the memories, the address signal generated by the address generation means provided in the microprocessor and the test address signal supplied from the external circuit. Thereby, the address of memories can be accessed directly from the external circuit for the test of memories. Moreover, the microprocessor is provided with the test bus through which the signal transmitted between the function blocks in the microprocessor is input or output from or to the external circuit. Accordingly, the function block can be tested easily.

摘要翻译： 具有多个存储器的微处理器包括：地址选择装置，用于向存储器选择性地提供由微处理器中提供的地址产生装置产生的地址信号和从外部电路提供的测试地址信号。 因此，可以从外部电路直接访问存储器的地址以进行存储器的测试。 此外，微处理器设置有测试总线，通过该测试总线在微处理器中的功能块之间传输的信号通过其输入或输出到外部电路。 因此，可以容易地测试功能块。