公开(公告)号：US20100182828A1

公开(公告)日：2010-07-22

申请号：US12688886

申请日：2010-01-17

申请人： Akio SHIMA ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

发明人： Akio SHIMA ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

IPC分类号： G11C11/00 ,  H01L47/00 ,  G11C8/00

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1683

摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

摘要翻译： 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以构成三维存储器 单元格阵列。 存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。 通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

公开(公告)号：US20090267047A1

公开(公告)日：2009-10-29

申请号：US12430539

申请日：2009-04-27

申请人： Yoshitaka SASAGO ,  Riichiro TAKEMURA ,  Masaharu KINOSHITA ,  Toshiyuki MINE ,  Akio SHIMA ,  Hideyuki MATSUOKA ,  Mutsuko HATANO ,  Norikatsu TAKAURA

发明人： Yoshitaka SASAGO ,  Riichiro TAKEMURA ,  Masaharu KINOSHITA ,  Toshiyuki MINE ,  Akio SHIMA ,  Hideyuki MATSUOKA ,  Mutsuko HATANO ,  Norikatsu TAKAURA

IPC分类号： H01L47/00

CPC分类号： H01L27/2481 ,  H01L21/02532 ,  H01L21/02675 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146

摘要： The present invention can promote the large capacity, high performance and high reliability of a semiconductor memory device by realizing high-performance of both the semiconductor device and a memory device when the semiconductor memory device is manufactured by stacking a memory device such as ReRAM or the phase change memory and the semiconductor device. After a polysilicon forming a selection device is deposited in an amorphous state at a low temperature, the crystallization of the polysilicon and the activation of impurities are briefly performed with heat treatment by laser annealing. When laser annealing is performed, the recording material located below the silicon subjected to the crystallization is completely covered with a metal film or with the metal film and an insulating film, thereby making it possible to suppress a temperature increase at the time of performing the annealing and to reduce the thermal load of the recording material.

摘要翻译： 本发明可以通过实现半导体器件和存储器件的高性能来促进半导体存储器件的大容量，高性能和高可靠性，当半导体存储器件通过堆叠诸如ReRAM的存储器件或 相变存储器和半导体器件。 在低温下以非晶态沉积形成选择器件的多晶硅后，通过激光退火的热处理来简单地进行多晶硅的结晶化和杂质的活化。 当进行激光退火时，位于被结晶的硅下方的记录材料完全被金属膜或金属膜和绝缘膜覆盖，从而可以抑制进行退火时的温度升高 并降低记录材料的热负荷。

公开(公告)号：US20120074368A1

公开(公告)日：2012-03-29

申请号：US13181663

申请日：2011-07-13

申请人： Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Mitsuharu TAI ,  Akio SHIMA ,  Takashi KOBAYASHI

发明人： Yoshitaka SASAGO ,  Masaharu KINOSHITA ,  Mitsuharu TAI ,  Akio SHIMA ,  Takashi KOBAYASHI

IPC分类号： H01L47/00 ,  H01L21/3205

CPC分类号： H01L27/2445 ,  H01L27/0688 ,  H01L27/1021 ,  H01L45/1226 ,  H01L45/144

摘要： A semiconductor memory device having a diode and a transistor connected in series, which prevents carriers from going from the diode into the transistor, thereby reducing the possibility of transistor deterioration. A structure to annihilate carriers from the diode is provided between a channel layer of the transistor and a diode semiconductor layer of the diode where the carriers are generated.

摘要翻译： 具有串联连接的二极管和晶体管的半导体存储器件，其防止载流子从二极管进入晶体管，从而降低晶体管劣化的可能性。 在晶体管的沟道层和二极管的二极管半导体层之间提供从二极管湮灭载流子的结构，其中产生载流子。

公开(公告)号：US20110297911A1

公开(公告)日：2011-12-08

申请号：US13118402

申请日：2011-05-28

申请人： Akio SHIMA ,  Yoshitska Sasago ,  Toshiyuki Mine ,  Masaharu Kinoshita

发明人： Akio SHIMA ,  Yoshitska Sasago ,  Toshiyuki Mine ,  Masaharu Kinoshita

IPC分类号： H01L47/00

CPC分类号： H01L27/2454 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A technique used for a semiconductor device formed by stacking multiple structural bodies each having a semiconductor device, for preventing generation of thermal load on a structural body at a lower layer which is caused by a laser used in a step of forming a structural body at an upper layer. In a phase-change memory including multiple stacked memory matrices, a metal film is disposed between a memory matrix at a lower layer and a memory matrix at an upper layer formed over the memory matrix at the lower layer, in which the laser used for forming the memory matrix is reflected at the metal film and prevented from transmitting the metal film, thereby preventing the phase-change material layer, etc. in the memory matrix at the lower layer from being directly heated excessively by the laser.

摘要翻译： 一种用于半导体器件的技术，该半导体器件通过堆叠多个具有半导体器件的结构体而形成，用于防止由在用于形成结构体的步骤中使用的激光器引起的下层的结构体上的热负荷的产生 上层。 在包括多个堆叠的存储器矩阵的相变存储器中，金属膜设置在下层的存储矩阵和在下层的存储矩阵上形成的上层的存储矩阵之间，其中用于形成的激光 存储矩阵在金属膜处被反射并且防止金属膜透射，从而防止下层的存储矩阵中的相变材料层等被激光过度直接加热。

公开(公告)号：US20120149143A1

公开(公告)日：2012-06-14

申请号：US13303227

申请日：2011-11-23

申请人： Keiji WATANABE ,  Toshiyuki MINE ,  Akio SHIMA ,  Tomoko SEKIGUCHI ,  Ryuta TSUCHIYA

发明人： Keiji WATANABE ,  Toshiyuki MINE ,  Akio SHIMA ,  Tomoko SEKIGUCHI ,  Ryuta TSUCHIYA

IPC分类号： H01L31/18

CPC分类号： H01L31/02168 ,  B82Y20/00 ,  H01L31/0352 ,  H01L31/035236 ,  H01L31/055 ,  H01L31/075 ,  H01L31/1872 ,  Y02E10/52 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

摘要： In the existent method for manufacturing a solar cell, manufacture of a solar cell having a quantum well having a crystalline well layer and capable of controlling the thickness of the well layer was difficult. A quantum well having an amorphous well layer, comprising a barrier layer and an amorphous well layer is formed and then the quantum well having the amorphous well layer is annealed thereby crystallizing the amorphous well layer to form a quantum well having a crystalline well layer. By applying energy density applied to the amorphous well layer at an energy density of 1.26 J/mm2 or more and 28.8 J/mm2 or less, the crystalline well layer can be formed and the lamination structure of the quantum well can be maintained simultaneously.

摘要翻译： 在制造太阳能电池的现有方法中，难以制造具有具有结晶阱层并能够控制阱层的厚度的量子阱的太阳能电池。 形成具有非晶阱层的量子阱，其包含阻挡层和非晶阱层，然后对具有非晶阱层的量子阱退火，从而使非晶阱层结晶，形成具有结晶阱层的量子阱。 通过以1.26J / mm 2以上且28.8J / mm 2以下的能量密度施加到非晶质阱层的能量密度，可以形成结晶阱层，同时可以维持量子阱的层叠结构。

公开(公告)号：US20110001191A1

公开(公告)日：2011-01-06

申请号：US12830379

申请日：2010-07-05

申请人： Akio SHIMA ,  Nobuyuki SUGII

发明人： Akio SHIMA ,  Nobuyuki SUGII

IPC分类号： H01L29/786 ,  H01L21/84

CPC分类号： H01L29/78618 ,  H01L21/268 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/458

摘要： A semiconductor device which includes: a semiconductor layer formed over an insulating layer over a semiconductor substrate; a gate electrode disposed over the semiconductor layer through a gate insulator; a sidewall insulator formed along the gate insulating film and a sidewall of the gate electrode; a source/drain layer including an alloy layer whose bottom surface is in contact with the insulating layer; and an impurity-doped layer which is segregated in a self-aligned manner in an interface between the alloy layer and the semiconductor layer and has a face for junction with a channel region formed along a crystal orientation plane of the semiconductor layer.

摘要翻译： 一种半导体器件，包括：形成在半导体衬底上的绝缘层上的半导体层; 栅电极，其通过栅极绝缘体设置在所述半导体层上; 沿栅极绝缘膜和栅电极的侧壁形成的侧壁绝缘体; 源极/漏极层，其包括其底表面与绝缘层接触的合金层; 以及杂质掺杂层，其在合金层和半导体层之间的界面中以自对准的方式分离，并且具有用于与沿着半导体层的晶体取向平面形成的沟道区的结的面。