公开(公告)号：US07212205B2

公开(公告)日：2007-05-01

申请号：US10703508

申请日：2003-11-10

申请人： Akira Uesaki ,  Akio Nishimura ,  Tadashi Kobayashi ,  Yoshiyuki Mochizuki ,  Kazu Segawa ,  Makoto Yamakura ,  Kazutaka Nishio ,  Hitoshi Araki ,  Kenji Nishimura

发明人： Akira Uesaki ,  Akio Nishimura ,  Tadashi Kobayashi ,  Yoshiyuki Mochizuki ,  Kazu Segawa ,  Makoto Yamakura ,  Kazutaka Nishio ,  Hitoshi Araki ,  Kenji Nishimura

IPC分类号： G06T15/00

CPC分类号： G06T17/30

摘要： A curved surface image processing apparatus 100 according to the present invention that can render an object at higher speed and in higher quality by performing image processing using NURBS data includes: a data input unit 101 for receiving NURBS data; a coordinate transformation unit 102 for performing coordinate transformation on NURBS data; an animation control unit 103 for controlling animation data of each frame to be rendered; a data transformation unit 104 for transforming NURBS data into rational Bezier data; a patch division unit 105 for subdividing a rational Bezier surface patch; a normal determination unit 106 for calculating normals of control points of a divided surface patch; a perspective transformation unit 107 for performing perspective transformation on a divided surface patch; and a rendering unit 108 for rendering a surface patch.

摘要翻译： 根据本发明的能够通过使用NURBS数据进行图像处理，能够以更高的速度和更高质量呈现物体的曲面图像处理装置100包括：数据输入单元101，用于接收NURBS数据; 用于对NURBS数据执行坐标变换的坐标变换单元102; 用于控制要渲染的每帧的动画数据的动画控制单元103; 数据转换单元104，用于将NURBS数据变换为有理Bezier数据; 用于细分有理Bezier曲面贴片的贴片分割单元105; 用于计算分割表面贴片的控制点的法线的正常确定单元106; 透视变换单元107，用于对分割的表面贴片执行透视变换; 以及用于渲染表面贴片的渲染单元108。

公开(公告)号：US07649531B2

公开(公告)日：2010-01-19

申请号：US11630102

申请日：2005-09-06

申请人： Yudai Ishibashi ,  Tadashi Kobayashi ,  Makoto Yamakura

发明人： Yudai Ishibashi ,  Tadashi Kobayashi ,  Makoto Yamakura

IPC分类号： G06T15/00

CPC分类号： G06T11/40

摘要： An image generation device includes a memory in which a burst length, which is the smallest unit of read/write processing, is large; and an image generation device in which processing efficiency at the time of a memory access does not decrease, even in the case of accessing a rendering buffer for rendering a polygon. Image data is stored in a rendering buffer in block units made up of plural pixels, and image data of pixels corresponding to the polygon is stored in a serial region of the rendering buffer. A valid pixel flag indicating that a valid pixel is present within the block is stored in the rendering information buffer. The rendering buffer is accessed as little as possible based on placement of the valid pixel flags within the block.

摘要翻译： 图像生成装置包括作为读/写处理的最小单位的突发长度大的存储器; 以及即使在访问用于渲染多边形的渲染缓冲器的情况下，存储器访问时的处理效率也不降低的图像生成装置。 图像数据以由多个像素构成的块单位存储在呈现缓冲器中，并且与多边形相对应的像素的图像数据被存储在呈现缓冲器的串行区域中。 指示该块内存在有效像素的有效像素标志被存储在该呈现信息缓冲器中。 基于块内有效像素标记的放置，尽可能少地访问渲染缓冲区。

公开(公告)号：US20080055309A1

公开(公告)日：2008-03-06

申请号：US11630102

申请日：2005-09-06

申请人： Yudai Ishibashi ,  Tadashi Kobayashi ,  Makoto Yamakura

发明人： Yudai Ishibashi ,  Tadashi Kobayashi ,  Makoto Yamakura

IPC分类号： G06T15/00

CPC分类号： G06T11/40

摘要： In an image generation device that includes a memory in which a burst length, which is the smallest unit of read/write processing, is large, an image generation device in which processing efficiency at the time of a memory access does not decrease, even in the case of accessing a rendering buffer for rendering a polygon. Image data is stored in the rendering buffer in block units made up of plural pixels. At this time, image data of pixels corresponding to the polygon is stored in a serial region of the rendering buffer. A valid pixel flag indicating that a valid pixel is present within the block is stored in a rendering information buffer. The rendering buffer is accessed as little as possible based on placement of the valid pixel flags within the block.

摘要翻译： 在包括作为读/写处理的最小单位的突发长度大的存储器的图像生成装置中，即使在存储器访问时的处理效率也不降低的图像生成装置 访问用于渲染多边形的渲染缓冲区的情况。 图像数据以由多个像素组成的块单元存储在渲染缓冲器中。 此时，与多边形对应的像素的图像数据被存储在呈现缓冲器的串行区域中。 指示在块内存在有效像素的有效像素标志被存储在呈现信息缓冲器中。 基于块内有效像素标记的放置，尽可能少地访问渲染缓冲区。

公开(公告)号：US06924824B2

公开(公告)日：2005-08-02

申请号：US09936172

申请日：2001-01-15

申请人： Katsumi Adachi ,  Makoto Yamakura ,  Kunio Sekimoto ,  Yoshinori Kobayashi

发明人： Katsumi Adachi ,  Makoto Yamakura ,  Kunio Sekimoto ,  Yoshinori Kobayashi

IPC分类号： G09G3/20 ,  G09G3/32 ,  G09G3/36 ,  G09G3/28

CPC分类号： G09G3/20 ,  G09G3/2011 ,  G09G3/2022 ,  G09G3/2029 ,  G09G3/2033 ,  G09G3/2081 ,  G09G3/3688 ,  G09G2300/0842 ,  G09G2310/0216 ,  G09G2310/0227 ,  G09G2310/027 ,  G09G2320/0247 ,  G09G2320/0261 ,  G09G2320/0266 ,  G09G2330/021

摘要： The present invention provides a method of driving an active matrix display device in which one frame comprises a plurality of sub-frames each comprising a write time and a hold time and gray scale driving is brought about by the cumulative effect of the hold times. Gray scale display driving is carried out by randomly scanning scan lines other than one predetermined scan line in a predetermined sequence in the hold time of each sub-frame corresponding to the one predetermined scan line so that any one sub-frame is not written to any one scan line more than once and one frame is such that in each of the scan lines, the writings and the hold time of each of the sub-frames is ensured to bring about gray scale display. Through this means, the frame period is shortened.

摘要翻译： 本发明提供了一种驱动有源矩阵显示装置的方法，其中一帧包括多个子帧，每个子帧包括写入时间和保持时间，并且由保持时间的累积效应引起灰度驱动。 灰度级显示驱动通过在与一条预定扫描线对应的每个子帧的保持时间内以预定顺序随机扫描除一条预定扫描线以外的扫描线，以便任何一个子帧不被写入任何一个子帧 一个扫描线不止一次，一个帧使得在每条扫描线中，确保每个子帧的写入和保持时间带来灰度显示。 通过这种方式，帧周期缩短。

公开(公告)号：US20050001857A1

公开(公告)日：2005-01-06

申请号：US10481566

申请日：2002-06-21

申请人： Tomoki Nakakita ,  Makoto Yamakura ,  Mika Nakamura ,  Takashi Koizumi

发明人： Tomoki Nakakita ,  Makoto Yamakura ,  Mika Nakamura ,  Takashi Koizumi

IPC分类号： G09G5/00 ,  G09G5/39 ,  G09G5/10

CPC分类号： G09G5/39 ,  G09G5/003 ,  G09G2330/021 ,  G09G2340/0428 ,  G09G2360/12 ,  G09G2360/18

摘要： An image display device of this invention includes image memory (3) which is constructed of SRAM and which does not need any refreshing operation, image memory (3) being composed of MSB division memory (13) for storing MSB data of each pixel data item and lower-order bit division memory (14) for storing lower-order bit data other than the MSB data. In a normal mode MSB division memory (13) and lower-order bit division memory (14) are driven to cause the MSB data and the lower-order bit data to be read/written, whereas in an electric power saving mode only MSB division memory (13) is driven with lower-order bit division memory (14) remaining undriven to cause the MSB data to be read/written.

摘要翻译： 本发明的图像显示装置包括由SRAM构成并且不需要任何刷新操作的图像存储器（3），图像存储器（3）由用于存储每个像素数据项的MSB数据的MSB分割存储器（13）组成 和低位比特分割存储器（14），用于存储除了MSB数据以外的低阶位数据。 在正常模式下，MSB分割存储器（13）和低位分位存储器（14）被驱动以使得MSB数据和低位位数据被读/写，而在省电模式中仅MSB分频 存储器（13）由低位比特分割存储器（14）驱动，剩余不起来以使得MSB数据被读/写。

公开(公告)号：US08817034B2

公开(公告)日：2014-08-26

申请号：US13003352

申请日：2010-05-20

申请人： Makoto Yamakura

发明人： Makoto Yamakura

IPC分类号： G09G5/36 ,  G06F13/372 ,  G06T11/00

CPC分类号： G06T11/00

摘要： Provided is a graphics rendering device that includes a frame data generation unit, access pattern setting unit, and frame data writing unit. The frame data generation unit generates, from part of stencil data, a part of frame data composed of a piece of second pixel information corresponding to a predetermined number of pixels in accordance with a first access pattern and an anti-alias pattern used in generating pieces of second pixel information. The access pattern setting unit sets, in accordance with the first access pattern and the anti-alias pattern, a second access pattern indicating pieces of second pixel information accessible by a single access to the frame buffer. The frame data writing unit writes in the frame buffer, when the frame data generation unit has generated a number of pieces of second pixel information indicated by the second access pattern, a part of the frame data corresponding to the number of pieces of second pixel information in accordance with the second access pattern.

摘要翻译： 提供了一种包括帧数据生成单元，访问模式设置单元和帧数据写入单元的图形呈现设备。 帧数据生成单元根据第一访问模式和在生成部件中使用的抗混叠图案，从模板数据的一部分生成由与预定数量的像素对应的第二像素信息构成的帧数据的一部分 的第二像素信息。 访问模式设置单元根据第一访问模式和抗混叠模式，设置指示通过对帧缓冲器的单一访问可访问的第二像素信息的第二访问模式。 帧数据写入单元写入帧缓冲器，当帧数据生成单元生成由第二访问模式指示的多个第二像素信息时，与第二像素信息的数量相对应的一部分帧数据 按照第二种访问模式。

公开(公告)号：US20110115813A1

公开(公告)日：2011-05-19

申请号：US13003352

申请日：2010-05-20

申请人： Makoto Yamakura

发明人： Makoto Yamakura

IPC分类号： G06T5/00

CPC分类号： G06T11/00

摘要： Provided is a graphics rendering device that includes a frame data generation unit, access pattern setting unit, and frame data writing unit. The frame data generation unit generates, from part of stencil data, a part of frame data composed of a piece of second pixel information corresponding to a predetermined number of pixels in accordance with a first access pattern and an anti-alias pattern used in generating pieces of second pixel information. The access pattern setting unit sets, in accordance with the first access pattern and the anti-alias pattern, a second access pattern indicating pieces of second pixel information accessible by a single access to the frame buffer. The frame data writing unit writes in the frame buffer, when the frame data generation unit has generated a number of pieces of second pixel information indicated by the second access pattern, a part of the frame data corresponding to the number of pieces of second pixel information in accordance with the second access pattern.

摘要翻译： 提供了一种包括帧数据生成单元，访问模式设置单元和帧数据写入单元的图形呈现设备。 帧数据生成单元根据第一访问模式和在生成部件中使用的抗混叠图案，从模板数据的一部分生成由与预定数量的像素对应的第二像素信息构成的帧数据的一部分 的第二像素信息。 访问模式设置单元根据第一访问模式和抗混叠模式，设置指示通过对帧缓冲器的单一访问可访问的第二像素信息的第二访问模式。 帧数据写入单元写入帧缓冲器，当帧数据生成单元生成由第二访问模式指示的多个第二像素信息时，与第二像素信息的数量相对应的一部分帧数据 按照第二种访问模式。

公开(公告)号：US06373458B1

公开(公告)日：2002-04-16

申请号：US09432605

申请日：1999-11-03

申请人： Makoto Yamakura ,  Katsumi Adachi

发明人： Makoto Yamakura ,  Katsumi Adachi

IPC分类号： G09G336

CPC分类号： G09G3/3677 ,  G09G3/2011 ,  G09G3/3648 ,  G09G3/3688 ,  G09G5/18 ,  G09G2300/0408 ,  G09G2310/027 ,  G11C19/28

摘要： The motion circuit of the present invention is an on-board driver circuit which is composed of polycrystal silicon semiconductor layers formed on a substrate, and which is provided with a first latch circuit for latching one of a normal phase and reverse phase clock signals having a clock skew using a clock signal and for outputting it to a shift register, and a second latch circuit for latching the other one of the normal phase and reverse phase clock signals using a clock signal and for outputting to the shift register. The latch operations of the first and second latch circuits are timed to make the two clock signals have reverse polarities. Consequently, it is realized to provide a motion circuit performing stable circuit operations without malfunctions, by preventing the occurrence of the fail phenomenon due to a skew between the normal phase and reverse phase clock signals which drive the shift register. It is also realized to provide an on-board driver circuit for a liquid crystal display panel by employing the motion circuit.

摘要翻译： 本发明的运动电路是由在基板上形成的多晶硅半导体层构成的板载驱动电路，其具有用于锁存正相和反相时钟信号之一的第一锁存电路， 使用时钟信号的时钟偏移并将其输出到移位寄存器;以及第二锁存电路，用于使用时钟信号锁存正常相位和反相时钟信号中的另一个，并用于输出到移位寄存器。 第一和第二锁存电路的锁存操作被定时以使得两个时钟信号具有相反的极性。 因此，通过防止由于驱动移位寄存器的正相和反相时钟信号之间的偏斜引起的故障现象的发生，实现了提供一种运行电路，而不产生故障。 还实现了通过使用运动电路来提供用于液晶显示面板的板上驱动电路。