公开(公告)号：US20050036502A1

公开(公告)日：2005-02-17

申请号：US10895159

申请日：2004-07-20

Applicant: Alain Blanc ,  Rene Glaise ,  Francois Maut ,  Michel Poret

Inventor： Alain Blanc ,  Rene Glaise ,  Francois Maut ,  Michel Poret

IPC: H04L12/43 ,  H04L12/56

CPC classification number: H04L49/9036 ,  H04L49/201 ,  H04L49/3036 ,  H04L49/3045 ,  H04L49/90

Abstract: A system and a method to avoid packet traffic congestion in a shared memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers and handling unicast as well as multicast traffic. According to the invention, the virtual output queuing (VOQ) of all ingress adapters of a packet switch fabric are collapsed into its central switch core to allow an efficient flow control. The transmission of data packets from an ingress buffer to the switch core is subject to a mechanism of request/acknowledgment. Therefore, a packet is transmitted from a virtual output queue to the memory shared switch core only if the switch core can send it to the corresponding egress buffer. A token based mechanism allows the switch core to determine the egress buffer's level of occupation. Therefore, since the switch core knows the states of the input and output adapters, it is able to optimize packet switching and to avoid packet congestion. Furthermore, since a packet is admitted in the switch core only if it can be transmitted to the corresponding egress buffer, the shared memory is reduced.

Abstract translation: 一种避免共享存储交换机核心中的数据包流量拥塞的系统和方法，同时显着减少交换机核心和相关联的出口缓冲区中的共享存储器的数量以及处理单播以及组播流量。 根据本发明，分组交换结构的所有入口适配器的虚拟输出排队（VOQ）被折叠到其中央交换机核心中以允许有效的流控制。 数据包从入口缓冲区传输到交换机核心受到请求/确认机制的约束。 因此，只有当交换机核心才能将其发送到对应的出口缓冲区时，才将数据包从虚拟输出队列发送到存储器共享交换机内核。 基于令牌的机制允许交换机核心确定出口缓冲区的占用水平。 因此，由于交换机核心知道输入和输出适配器的状态，因此能够优化分组交换并避免分组拥塞。 此外，由于分组只有在可以发送到对应的出口缓冲器的情况下才允许在交换机核心中，所以共享存储器被减少。

公开(公告)号：US20080013548A1

公开(公告)日：2008-01-17

申请号：US11852661

申请日：2007-09-10

Applicant: Rene Glaise ,  Alain Blanc ,  Francois Maut ,  Michel Poret

Inventor： Rene Glaise ,  Alain Blanc ,  Francois Maut ,  Michel Poret

IPC: H04L12/56

CPC classification number: H04L49/15 ,  H04L49/103 ,  H04L49/1523 ,  H04L49/201 ,  H04L49/253 ,  H04L49/90

Abstract: A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.

Abstract translation: 包括输入和输出端口的高速数据分组交换机以及将每个输入端口链接到每个输出端口的交换结构，其中输入和输出端口之间的每个连接包括动态缓冲存储器，用于存储至少一个数据分组用于最小指定的存储时间 被披露。 当通过输入端口接收到数据包时，它被写入连接到该输入端口的所有单独的动态存储器缓冲器中，以便具有输入数据包的副本准备通过任何输出端口来支持单播，多播和广播 交通。 给定数据包交换机的架构及其控制算法，动态内存缓冲区既不需要刷新，也不需要在读取后恢复其内容。

公开(公告)号：US08085789B2

公开(公告)日：2011-12-27

申请号：US12365091

申请日：2009-02-03

Applicant: Alain Blanc ,  Rene Glaise ,  Francois Le Maut ,  Michel Poret

Inventor： Alain Blanc ,  Rene Glaise ,  Francois Le Maut ,  Michel Poret

IPC: H04L12/28

CPC classification number: H04L49/3027 ,  H04L49/103 ,  H04L49/201 ,  H04L49/3045

Abstract: A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism is disclosed. An egress location for an ingress port is selected based on degrees of freedom for the selection mechanism. The degree of freedom can be derived from the collapsed virtual output queuing array by determining a number of egress locations to which an ingress port may send packets and determining a number of ingress ports from which an egress location can receive packets. Analyzing all the queued packets for assignment to an egress location, starting with a lesser degree of freedom and ending with a greater degree of freedom provides efficient switching allocations and acknowledgements.

Abstract translation: 公开了一种使用请求/确认机制来选择在折叠的虚拟输出排队阵列（cVOQ）切换核心中切换的分组的方法。 基于选择机制的自由度选择入口端口的出口位置。 可以通过确定进入端口可以发送分组的出口位置的数量并确定出口位置可以从哪个入口端口接收分组的数目的入口端口，从折叠的虚拟输出排队阵列导出自由度。 分析所有排队的分组以分配到出口位置，以较小的自由度开始，并以更大的自由度结束，从而提供有效的切换分配和确认。

公开(公告)号：US07430167B2

公开(公告)日：2008-09-30

申请号：US10711320

申请日：2004-09-10

Applicant: Rene Glaise ,  Alain Blanc ,  Francois Le Maut ,  Michel Poret

Inventor： Rene Glaise ,  Alain Blanc ,  Francois Le Maut ,  Michel Poret

IPC: G06F11/00

CPC classification number: H04L47/125 ,  H04L49/1523 ,  H04L49/25 ,  H04L49/30 ,  H04L49/3045

Abstract: A method and a system to adapt the load balancing of the incoming traffic over the planes of a parallel packet switch (PPS) on the basis of the monitoring of requests and acknowledgments exchanged between ingress port adapters and arrays of collapsed virtual output queues (cVOQ) situated within the plane switch cores is disclosed. According to the invention, at least one counter is associated, in each ingress port-adapter, to each individual switching plane or device to be monitored. Each of these counters is incremented when a request is sent to the corresponding individual switching plane or device and decremented when an acknowledgment is received from this individual switching plane or device. When the range of values taken by the counters of a same ingress port-adapter reaches a predetermined threshold, less (or none) incoming traffic is further transmitted to the individual switching plane or device associated to the higher value counter. An alarm signal is possibly raised too e.g., for replacing the defective individual switching plane or device.

Abstract translation: 基于在入口端口适配器和折叠虚拟输出队列（cVOQ）阵列之间交换的请求和确认的监视来适应并行分组交换机（PPS）的平面上的入局业务的负载平衡的方法和系统， 位于平面开关芯内。 根据本发明，至少一个计数器在每个入口端口适配器中被关联到要监视的每个单独的切换平面或设备。 当将请求发送到相应的单独的交换平面或设备时，这些计数器中的每一个递增，并且当从该单独的交换平面或设备接收到确认时递减。 当相同入口端口适配器的计数器所取值的范围达到预定阈值时，较少（或无））进入流量进一步传输到与较高值计数器相关联的单独交换平面或设备。 也可能引起报警信号，例如用于更换有缺陷的单独开关平面或装置。

公开(公告)号：US07773602B2

公开(公告)日：2010-08-10

申请号：US12123602

申请日：2008-05-20

Applicant: Alain Blanc ,  Rene Glaise ,  Michel Poret ,  Rene Gallezot

Inventor： Alain Blanc ,  Rene Glaise ,  Michel Poret ,  Rene Gallezot

IPC: H04L12/28

CPC classification number: H04L67/1002 ,  H04L47/50 ,  H04L49/1523 ,  H04L49/3045 ,  H04L49/552 ,  H04L49/9094

Abstract: An embodiment of the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter has a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location, a controller, and a determination means coupled to a storing means and extracting means.

Abstract translation: 该系统的一个实施例在具有至少一个出口适配器的并行分组交换机体系结构中操作，所述出口适配器布置成接收从多个入口适配器发出的数据分组，并且通过多个独立交换平面切换。 每个接收到的数据分组属于多个序列中的一个数据分组序列，其中数据分组根据数据分组的至少优先级分配的分组序列号（PSN）进行编号。 由至少一个出口适配器接收的每个数据分组具有源标识符，用于标识从其发出的入口适配器。 用于恢复接收到的数据分组的序列的系统在出口适配器内操作，并且包括用于在分配的分组缓冲器位置临时存储每个接收的数据分组的缓冲器，控制器和耦合到存储装置和提取装置的确定装置。

公开(公告)号：US20090141733A1

公开(公告)日：2009-06-04

申请号：US12365091

申请日：2009-02-03

Applicant: Alain Blanc ,  Rene Glaise ,  Francois Le Maut ,  Michel Poret

Inventor： Alain Blanc ,  Rene Glaise ,  Francois Le Maut ,  Michel Poret

IPC: H04L12/56

CPC classification number: H04L49/3027 ,  H04L49/103 ,  H04L49/201 ,  H04L49/3045

Abstract: A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism. According to the method, an efficient set of virtual output queues (at most one virtual output queue per ingress adapter) is selected, while keeping the algorithm simple enough to allow its implementation in fast state machines. For determining a set of virtual output queues that are each authorized to send a packet, the algorithm is based upon degrees of freedom characterizing states of ingress and egress adapters. For example, the degree of freedom, derived from the collapsed virtual output queuing array, could represent the number of egress ports to which an ingress port may send packet, or the number of ingress ports from which an egress port may receive packets, at a given time. Analyzing all the ingress ports holding at least one data packet, from the lesser degree of freedom to the greater degree of freedom, the algorithm determines as many virtual output queues as possible, in the limit of the number of ingress ports (an ingress port may send only one packet per packet-cycle).

Abstract translation: 一种用于使用请求/确认机制来选择在折叠虚拟输出排队阵列（cVOQ）切换核心中切换的分组的方法。 根据该方法，选择一组有效的虚拟输出队列（每个入口适配器最多有一个虚拟输出队列），同时保持算法足够简单，以允许其在快速状态机中实现。 为了确定每个被授权发送分组的一组虚拟输出队列，该算法基于入射和出口适配器状态的自由度。 例如，从折叠的虚拟输出排队阵列导出的自由度可以表示入口端口可以发送分组的出口端口的数量，或出口端口可以从其接收分组的入口端口的数量， 给定时间 分析至少一个数据包的入口端口，从较小的自由度到较大的自由度，该算法在入口端口数量的限制中尽可能地确定尽可能多的虚拟输出队列（入口端口可能 每个分组周期只发送一个分组）。

公开(公告)号：US20080267206A1

公开(公告)日：2008-10-30

申请号：US12123602

申请日：2008-05-20

Applicant: Alain Blanc ,  Rene Glaise ,  Michel Poret ,  Rene Gallezot

Inventor： Alain Blanc ,  Rene Glaise ,  Michel Poret ,  Rene Gallezot

IPC: H04L12/56

CPC classification number: H04L67/1002 ,  H04L47/50 ,  H04L49/1523 ,  H04L49/3045 ,  H04L49/552 ,  H04L49/9094

Abstract: An embodiment of the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter has a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location, a controller, and a determination means coupled to a storing means and extracting means.

Abstract translation: 该系统的一个实施例在具有至少一个出口适配器的并行分组交换机体系结构中操作，所述出口适配器布置成接收从多个入口适配器发出的数据分组，并且通过多个独立交换平面切换。 每个接收到的数据分组属于多个序列中的一个数据分组序列，其中数据分组根据数据分组的至少优先级分配的分组序列号（PSN）进行编号。 由至少一个出口适配器接收的每个数据分组具有源标识符，用于标识从其发出的入口适配器。 用于恢复接收到的数据分组的序列的系统在出口适配器内操作，并且包括用于在分配的分组缓冲器位置临时存储每个接收的数据分组的缓冲器，控制器和耦合到存储装置和提取装置的确定装置。

公开(公告)号：US07400629B2

公开(公告)日：2008-07-15

申请号：US10723834

申请日：2003-11-26

Applicant: Alain Blanc ,  Rene Glaise ,  Michel Poret ,  Rene Gallezot

Inventor： Alain Blanc ,  Rene Glaise ,  Michel Poret ,  Rene Gallezot

IPC: H04L12/28

CPC classification number: H04L67/1002 ,  H04L47/50 ,  H04L49/1523 ,  H04L49/3045 ,  H04L49/552 ,  H04L49/9094

Abstract: A system for resequencing data packets is disclosed. In a preferred embodiment, the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter is further having a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location. Furthermore, controller to extract the packet sequence number, the source identifier and the priority level of each stored data packet. And determination means coupled to the storing means and to the extracting means allow to determine for each sequence of data packet the order of the data packets to be output from the egress adapter.

Abstract translation: 公开了一种用于重新排序数据包的系统。 在优选实施例中，系统以并行分组交换架构操作，其具有布置成接收从多个入口适配器发出并通过多个独立交换平面切换的数据分组的至少一个出口适配器。 每个接收到的数据分组属于多个序列中的一个数据分组序列，其中数据分组根据数据分组的至少优先级分配的分组序列号（PSN）进行编号。 由至少一个出口适配器接收的每个数据分组还具有源标识符以识别从其发出的入口适配器。 用于恢复接收到的数据分组的序列的系统在出口适配器内操作，并且包括用于在分配的分组缓冲器位置临时存储每个接收到的数据分组的缓冲器。 此外，控制器提取每个存储的数据包的包序列号，源标识符和优先级。 以及耦合到所述存储装置并且所述提取装置的确定装置允许针对每个数据分组序列确定要从所述出口适配器输出的数据分组的顺序。

公开(公告)号：US20050063301A1

公开(公告)日：2005-03-24

申请号：US10711320

申请日：2004-09-10

Applicant: Rene Glaise ,  Alain Blanc ,  Francois Le Maut ,  Michel Poret

Inventor： Rene Glaise ,  Alain Blanc ,  Francois Le Maut ,  Michel Poret

IPC: H04J3/14 ,  H04L12/54 ,  H04L12/56

CPC classification number: H04L47/125 ,  H04L49/1523 ,  H04L49/25 ,  H04L49/30 ,  H04L49/3045

Abstract: A method and a system to adapt the load balancing of the incoming traffic over the planes of a parallel packet switch (PPS) on the basis of the monitoring of requests and acknowledgments exchanged between ingress port adapters and arrays of collapsed virtual output queues (cVOQ) situated within the plane switch cores is disclosed. According to the invention, at least one counter is associated, in each ingress port-adapter, to each individual switching plane or device to be monitored. Each of these counters is incremented when a request is sent to the corresponding individual switching plane or device and decremented when an acknowledgment is received from this individual switching plane or device. When the range of values taken by the counters of a same ingress port-adapter reaches a predetermined threshold, less (or none) incoming traffic is further transmitted to the individual switching plane or device associated to the higher value counter. An alarm signal is possibly raised too e.g., for replacing the defective individual switching plane or device.

Abstract translation: 基于在入口端口适配器和折叠虚拟输出队列（cVOQ）阵列之间交换的请求和确认的监视来适应并行分组交换机（PPS）的平面上的入局业务的负载平衡的方法和系统， 位于平面开关芯内。 根据本发明，至少一个计数器在每个入口端口适配器中被关联到要监视的每个单独的切换平面或设备。 当将请求发送到相应的单独的交换平面或设备时，这些计数器中的每一个递增，并且当从该单独的交换平面或设备接收到确认时递减。 当相同入口端口适配器的计数器所取值的范围达到预定阈值时，较少（或无））进入流量进一步传输到与较高值计数器相关联的单独交换平面或设备。 也可能引起报警信号，例如用于更换有缺陷的单独开关平面或装置。

公开(公告)号：US20050053077A1

公开(公告)日：2005-03-10

申请号：US10894582

申请日：2004-07-20

Applicant: Alain Blanc ,  Rene Glaise ,  Francois Le Maut ,  Michel Poret

Inventor： Alain Blanc ,  Rene Glaise ,  Francois Le Maut ,  Michel Poret

IPC: H04L12/56 ,  H04L12/28

CPC classification number: H04L47/10 ,  H04L47/263 ,  H04L47/30 ,  H04L49/103 ,  H04L49/3027 ,  H04L49/3045

Abstract: A system and a method to avoid packet traffic congestion in a shared-memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers, is disclosed. According to the invention, the virtual output queuing (VOQ) of all ingress adapters of a packet switch fabric are collapsed into its central switch core to allow an efficient flow control. The transmission of packets from an ingress buffer to the switch core is subject to a mechanism of request/acknowledgment. Therefore, a packet is transmitted from a virtual output queue to the shared-memory switch core only if the switch core can actually forward it to the corresponding egress buffer. A token based mechanism allows the switch core to determine the egress buffer's level of occupation. Therefore, since the switch core knows the states of the input and output adapters, it is able to optimize packet switching and to avoid packet congestion. Furthermore, since a packet is admitted in the switch core only if it can be transmitted to the corresponding egress buffer, the shared memory is reduced.

Abstract translation: 公开了一种在共享存储器交换机核心中避免分组业务拥塞的系统和方法，同时显着地减少了交换机核心和相关联的出口缓冲器中的共享存储器的数量。 根据本发明，分组交换结构的所有入口适配器的虚拟输出排队（VOQ）被折叠到其中央交换机核心中以允许有效的流控制。 数据包从入口缓冲区传输到交换机核心受到请求/确认的机制。 因此，只有当交换机核心才能将其转发到相应的出口缓冲区时，才将数据包从虚拟输出队列传输到共享存储交换机内核。 基于令牌的机制允许交换机核心确定出口缓冲区的占用水平。 因此，由于交换机核心知道输入和输出适配器的状态，因此能够优化分组交换并避免分组拥塞。 此外，由于分组只有在可以发送到对应的出口缓冲器的情况下才允许在交换机核心中，所以共享存储器被减少。