公开(公告)号：US09348746B2

公开(公告)日：2016-05-24

申请号：US13826944

申请日：2013-03-14

Applicant: Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

Inventor： Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

IPC: G06F13/00 ,  G06F12/02 ,  G06F12/06 ,  G06F3/06 ,  G06F12/12

CPC classification number: G06F12/0246 ,  G06F3/0644 ,  G06F12/0253 ,  G06F12/0646 ,  G06F12/12

Abstract: A multi-later memory and method for operation is disclosed. The memory includes at least one flash memory die having multiple layers and a controller configured to execute block reclaim operations in a layer of the flash memory die until a net gain of at least one additional free block has been made in the layer. The method may include relocating data from reclaim blocks to relocation blocks within the same layer, or within a same partition in the same layer until a net gain of one free block has been achieved and an integer number of relocation blocks has been filled with relocated data. The method may also include moving data from reclaim blocks in a first layer into destination blocks in a second layer until a net gain of at least one free block has been achieved in the first layer.

Abstract translation: 公开了一种用于操作的多功能记忆体和方法。 存储器包括至少一个具有多个层的闪速存储器管芯和被配置为在闪速存储器管芯的层中执行块回收操作的控制器，直到在该层中已经进行了至少一个附加自由块的净增益。 该方法可以包括将数据从回收块重定位到相同层内的重定位块或同一层内的相同分区内，直到已经实现了一个空闲块的净增益，并且整数个重定位块已被重定位数据填充 。 该方法还可以包括将数据从第一层中的回收块移动到第二层中的目标块，直到在第一层中已经实现了至少一个空闲块的净增益。

公开(公告)号：US20140189207A1

公开(公告)日：2014-07-03

申请号：US13827038

申请日：2013-03-14

Applicant: Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

Inventor： Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F12/0253 ,  G06F2212/7205

Abstract: A multi-layer memory and method for performing background maintenance operations are disclosed. The memory includes a plurality of flash memory die having multiple layers, where each layer is made up of flash memory cells having a greater bit per cell storage capacity than then prior layer and each layer may have a plurality of partitions for different data types. A controller managing the flash memory die is configured to identify an idle die and determine if a layer in the die satisfies a background maintenance criterion. Upon identifying a layer satisfying the background maintenance criterion, the valid data from reclaim blocks in the layer is relocated into a relocation block in the same layer until the relocation block is filled and the background maintenance cycle ends.

Abstract translation: 公开了一种用于执行后台维护操作的多层存储器和方法。 存储器包括具有多个层的多个闪速存储器管芯，其中每个层由具有比之前的先前层更大的每个存储单元的位的闪存单元构成，并且每个层可以具有用于不同数据类型的多个分区。 管理闪存芯片的控制器被配置为识别空闲裸片，并且确定模具中的层是否满足背景维护标准。 在识别满足背景维护标准的层时，将层中回收块的有效数据重新定位到相同层中的重定位块中，直到重新定位块被填充并且后台维护周期结束。

公开(公告)号：US20140185376A1

公开(公告)日：2014-07-03

申请号：US13826848

申请日：2013-03-14

Applicant: Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

Inventor： Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G06F3/0613 ,  G06F3/0658 ,  G06F3/0688 ,  G06F12/0246 ,  G11C11/5628 ,  G11C2211/5641

Abstract: A mass storage memory system and method of operation is disclosed. The memory includes an interface adapted to receive data from a host, a plurality of flash memory die and a controller, where the controller is configured to receive a first command and read or write data synchronously across the plurality of die based on a first command, and to receive a second command and read or write data asynchronously and independently in each die based on a second command. The controller may program data in a maximum unit of programming for an individual one of the plurality of flash memory die. The controller may be a plurality of controllers each configured to select which die of an exclusive subset of die to write data based on characteristics of the die in the subset. The plurality of die may be multi-layer, and multi-partition per layer, flash memory die.

Abstract translation: 公开了大容量存储存储器系统和操作方法。 存储器包括适于从主机，多个闪存存储器模块和控制器接收数据的接口，其中控制器被配置为基于第一命令来接收第一命令并且跨多个管芯同步地读取或写入数据， 并且基于第二命令接收第二命令并且在每个管芯中异步且独立地读取或写入数据。 控制器可以针对多个闪存存储器芯片中的一个的最大编程单元编程数据。 控制器可以是多个控制器，每个控制器被配置为基于子集中的管芯的特性来选择管芯的独占子集的哪个管芯写入数据。 多个芯片可以是多层的，每层多分区，闪存芯片。

公开(公告)号：US09734050B2

公开(公告)日：2017-08-15

申请号：US13827038

申请日：2013-03-14

Applicant: Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

Inventor： Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F12/0253 ,  G06F2212/7205

Abstract: A multi-layer memory and method for performing background maintenance operations are disclosed. The memory includes a plurality of flash memory die having multiple layers, where each layer is made up of flash memory cells having a greater bit per cell storage capacity than then prior layer and each layer may have a plurality of partitions for different data types. A controller managing the flash memory die is configured to identify an idle die and determine if a layer in the die satisfies a background maintenance criterion. Upon identifying a layer satisfying the background maintenance criterion, the valid data from reclaim blocks in the layer is relocated into a relocation block in the same layer until the relocation block is filled and the background maintenance cycle ends.

公开(公告)号：US09666285B2

公开(公告)日：2017-05-30

申请号：US13826848

申请日：2013-03-14

Applicant: Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

Inventor： Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

IPC: G11C16/10 ,  G06F3/06 ,  G06F12/02 ,  G11C11/56

Abstract: A mass storage memory system and method of operation are disclosed. The memory system includes an interface adapted to receive data from a host system, a plurality of memory die and a controller, where the controller is configured to read or write data synchronously across a plurality of die connected to different channels based on a first command, and to read or write data asynchronously and independently in different die in the same channel based on a second command. The controller may program data in a maximum unit of programming for a single memory die. The controller may be a plurality of controllers each configured to select which die of an exclusive subset of die to write data based on characteristics of the die in the subset. The plurality of die may be multi-layer, and multi-partition per layer, flash memory die.

公开(公告)号：US20140189210A1

公开(公告)日：2014-07-03

申请号：US13827499

申请日：2013-03-14

Applicant: Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

Inventor： Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7204 ,  G06F2212/7208

Abstract: A flash memory system having unequal number of memory die and method for operation is disclosed. The memory includes a plurality of flash memory die distributed unevenly among different control lines, such that there are an unequal number of die between control lines. A total physical storage capacity of the plurality of flash memory die is greater than a total logical capacity such that the memory system is over provisioned with physical storage capacity. A logical address splitter directs data received from a host system and associated with host logical block addresses such that each control line only receives data associated with predetermined host logical block address ranges and directs the data such that a ratio of physical capacity to logical capacity is equal among each of the control lines, regardless of the different number of die, and associated different physical capacity per control line.

Abstract translation: 公开了一种具有不同数量的存储器管芯和操作方法的闪存系统。 存储器包括在不同控制线之间不均匀地分布的多个闪速存储器管芯，使得在控制线之间存在不相等数量的管芯。 多个闪存芯片的总物理存储容量大于总逻辑容量，使得存储器系统被过度配置具有物理存储容量。 逻辑地址分配器指导从主机系统接收的并与主机逻辑块地址相关联的数据，使得每个控制线仅接收与预定主机逻辑块地址范围相关联的数据，并引导数据，使得物理容量与逻辑容量之比相等 在每个控制线中，不考虑不同的管芯数量，以及每个控制线的相应不同的物理容量。

公开(公告)号：US08537613B2

公开(公告)日：2013-09-17

申请号：US13077487

申请日：2011-03-31

Applicant: Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

Inventor： Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C2211/5641 ,  G11C2211/5643

Abstract: A multi-later memory and method for operation is disclosed. The memory includes three or more layers, where each layer is made up of flash memory cells having a greater bit per cell storage capacity than then prior layer. The method may include the steps of directing host data directly into a first or second layer of the multi-layer memory upon receipt depending on a condition of the data. The method may also include copying data within a respective layer in a data relocation operation to generate more free blocks of memory so that data preferably stays within each layer, as well as transferring data from one layer to the next higher bit per cell layer when layer transfer criteria are met.

Abstract translation: 公开了一种用于操作的多功能记忆体和方法。 存储器包括三层或更多层，其中每层由具有比之前的先前层更大的每存储容量的闪存单元组成。 该方法可以包括以下步骤：根据数据的条件，将主机数据直接导入多层存储器的第一层或第二层。 该方法还可以包括在数据重定位操作中在相应层内复制数据以生成更多的空闲存储块，使得数据优选地保持在每一层内，并且当层（layer）时将数据从每个层传送到下一较高位 转移标准得到满足。

公开(公告)号：US09223693B2

公开(公告)日：2015-12-29

申请号：US13827499

申请日：2013-03-14

Applicant: Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

Inventor： Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7204 ,  G06F2212/7208

Abstract: A flash memory system having unequal number of memory die and method for operation are disclosed. The memory system includes a plurality of flash memory die distributed unevenly among different control lines, such that there are an unequal number of die between control lines. A total physical capacity of the plurality of flash memory die is greater than a total logical capacity such that the memory system is over provisioned with physical capacity. A logical address splitter directs data received from a host system and associated with host logical block addresses such that each control line only receives data associated with predetermined host logical block address ranges and directs the data such that a ratio of physical capacity to logical capacity is equal among each of the control lines, regardless of the different number of die and associated different physical capacity per control line.

Abstract translation: 公开了一种具有不等数量的存储器管芯和操作方法的闪存系统。 存储器系统包括在不同控制线之间不均匀地分布的多个闪速存储器管芯，使得在控制线之间存在不相等数量的管芯。 多个闪存芯片的总物理容量大于总逻辑容量，使得存储器系统过度提供物理容量。 逻辑地址分配器指导从主机系统接收的并与主机逻辑块地址相关联的数据，使得每个控制线仅接收与预定主机逻辑块地址范围相关联的数据，并引导数据，使得物理容量与逻辑容量之比相等 在每个控制线中，不管每个控制线的管芯数量和不同物理容量的数量不同。

公开(公告)号：US08873284B2

公开(公告)日：2014-10-28

申请号：US13827204

申请日：2013-03-14

Applicant: Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

Inventor： Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

IPC: G11C16/04

CPC classification number: G06F12/0246 ,  G06F2212/7205

Abstract: A multi-layer memory and method for operation is disclosed. The memory includes an interface, at least one flash memory die having a plurality of layers and a controller. The controller is configured to select an appropriate one of a predetermined number of program cycles for programming a fixed amount of host data, and for carrying out maintenance operations in one or more of the layers sufficient to permit a next host data write operation. The controller calculates an interleave ratio of maintenance operations to host data programming operations in each of the layers used in the determined programming cycle so that creation of free space is interspersed with host data writes in a steady manner during execution of the determined programming cycle.

Abstract translation: 公开了一种用于操作的多层存储器和方法。 存储器包括接口，至少一个具有多个层的闪存芯片和控制器。 控制器被配置为选择用于编程固定数量的主机数据的预定数量的编程周期中的适当的一个，并且用于在足以允许下一个主机数据写入操作的一个或多个层中执行维护操作。 控制器计算维护操作的交织比，以在所确定的编程周期中使用的每个层中的主机数据编程操作，从而在确定的编程周期的执行期间，以可靠的方式使主机数据写入分散。

公开(公告)号：US20140189206A1

公开(公告)日：2014-07-03

申请号：US13826944

申请日：2013-03-14

Applicant: Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

Inventor： Alan Welsh Sinclair ,  Nicholas James Thomas ,  Barry Wright

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/0644 ,  G06F12/0253 ,  G06F12/0646 ,  G06F12/12

Abstract: A multi-later memory and method for operation is disclosed. The memory includes at least one flash memory die having multiple layers and a controller configured to execute block reclaim operations in a layer of the flash memory die until a net gain of at least one additional free block has been made in the layer. The method may include relocating data from reclaim blocks to relocation blocks within the same layer, or within a same partition in the same layer until a net gain of one free block has been achieved and an integer number of relocation blocks has been filled with relocated data. The method may also include moving data from reclaim blocks in a first layer into destination blocks in a second layer until a net gain of at least one free block has been achieved in the first layer.

Abstract translation: 公开了一种用于操作的多功能记忆体和方法。 存储器包括至少一个具有多个层的闪速存储器管芯和被配置为在闪速存储器管芯的层中执行块回收操作的控制器，直到在该层中已经进行了至少一个附加自由块的净增益。 该方法可以包括将数据从回收块重新定位到相同层内的重定位块或同一层内的相同分区内，直到已经实现了一个空闲块的净增益，并且整数个重定位块已被重定位数据填充 。 该方法还可以包括将数据从第一层中的回收块移动到第二层中的目标块，直到在第一层中已经实现了至少一个空闲块的净增益。