公开(公告)号：US06294925B1

公开(公告)日：2001-09-25

申请号：US09440460

申请日：1999-11-15

申请人： Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

发明人： Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

IPC分类号： H03K19177

CPC分类号： H03K19/17728 ,  H03K17/163

摘要： An improved programmable logic device that generates output signals skewed in time includes a set of I/O cells and first and second logic circuits. Each logic circuit generates a logic output signal on a respective output line coupled to at least one of the I/O cells. A first delay element coupled to the output line of the first logic circuit is programmably operable to delay the output signal of the first logic circuit relative to the output signal of the second logic circuit in response to a first delay control signal. A second delay element coupled to the output line of the second logic circuit is programmably operable to delay the output signal of the second logic circuit relative to the output signal of the first logic circuit in response to a second delay control signal. Control circuitry generates the first and second delay control signals so as to prevent simultaneous switching of the logic output signals of the first and second logic circuits. This invention may be used to delay output signals which are not time-critical, allowing fast switching of the limited number of time-critical macrocell output signals.

摘要翻译： 产生在时间上偏斜的输出信号的改进的可编程逻辑器件包括一组I / O单元和第一和第二逻辑电路。 每个逻辑电路在耦合到至少一个I / O单元的相应输出线上产生逻辑输出信号。 耦合到第一逻辑电路的输出线的第一延迟元件可编程地用于响应于第一延迟控制信号而相对于第二逻辑电路的输出信号延迟第一逻辑电路的输出信号。 耦合到第二逻辑电路的输出线的第二延迟元件可编程地可操作地响应于第二延迟控制信号而延迟第二逻辑电路相对于第一逻辑电路的输出信号的输出信号。 控制电路产生第一和第二延迟控制信号，以防止第一和第二逻辑电路的逻辑输出信号的同时切换。 本发明可以用于延迟不是时间关键的输出信号，允许有限数量的时间关键的宏单元输出信号的快速切换。

公开(公告)号：US06229336B1

公开(公告)日：2001-05-08

申请号：US09186917

申请日：1998-11-06

申请人： Bradley Felton ,  Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

发明人： Bradley Felton ,  Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

IPC分类号： H03K19173

CPC分类号： H03K17/163 ,  H03K19/17744 ,  H03K19/17792

摘要： A programmable integrated circuit device includes a plurality of output terminals, each output terminal for use in transmitting a respective output signal. Timing control circuitry is connected to the output terminals. The timing control circuitry is operable to delay the output signal on each output terminal and is further operable to control a slew rate of the output signal on each output terminal.

摘要翻译： 可编程集成电路装置包括多个输出端子，每个输出端子用于发送相应的输出信号。 定时控制电路连接到输出端子。 定时控制电路可操作以延迟每个输出端上的输出信号，并且还可操作以控制每个输出端上的输出信号的转换速率。

公开(公告)号：US06255847B1

公开(公告)日：2001-07-03

申请号：US09083205

申请日：1998-05-21

申请人： Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

发明人： Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

IPC分类号： H03K19177

CPC分类号： H03K19/17728 ,  H03K17/163

摘要： An improved programmable logic device includes a set of I/O cells, a set of logic blocks, and a routing pool that provides connections among the logic blocks and the I/O cells. At least one of the logic blocks includes a programmable logic array that generates product term output signals on product term output lines. A first product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The first product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. Likewise, a second product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The second product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. The logic block further includes first and second output lines and a first programmable switching device that programmably couples the first output line to the output terminal of either the first or the second product term summing circuit. The logic block further includes a second programmable switching device that programmably couples the second output line to the output terminal of either the first or the second product term summing circuit. The programmable logic device has increased functional capacity. In addition, generating an interconnect solution to program the programmable logic device is made simpler by the present invention.

摘要翻译： 改进的可编程逻辑器件包括一组I / O单元，一组逻辑块和提供逻辑块和I / O单元之间的连接的路由池。 至少一个逻辑块包括在产品项输出线上产生产品项输出信号的可编程逻辑阵列。 第一乘积项求和电路具有输入端子，其中至少一个耦合到产品项输出线。 第一乘积项求和电路响应于至少一个乘积项输出信号在输出端产生输出信号。 类似地，第二乘积项求和电路具有输入端子，其中至少一个耦合到产品项输出线。 第二乘积项求和电路响应于至少一个乘积项输出信号在输出端产生输出信号。 逻辑块还包括第一和第二输出线以及可编程地将第一输出线耦合到第一或第二乘积项求和电路的输出端的第一可编程开关装置。 逻辑块还包括可编程地将第二输出线耦合到第一或第二乘积项求和电路的输出端的第二可编程开关装置。 可编程逻辑器件具有增加的功能容量。 此外，通过本发明使得生成用于编程可编程逻辑器件的互连解决方案变得更简单。

公开(公告)号：US6066977A

公开(公告)日：2000-05-23

申请号：US83336

申请日：1998-05-21

申请人： Bradley Felton ,  Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

发明人： Bradley Felton ,  Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

IPC分类号： H03K19/0185 ,  H03K17/16

CPC分类号： H03K19/018585

摘要： A circuit for providing programmable voltage output levels in a logic device includes a pull-up device for driving an output pad with either a first voltage output level or a second voltage output level. A charge pump generates a pumped voltage. A first clamp regulator, coupled to the charge pump and the pull-up device, receives a first reference signal. The first clamp regulator, in response to the first reference signal, generates a first voltage from which the first voltage output level is derived. A second clamp regulator, coupled to the pull-up device, receives a second reference signal. In response to the second reference signal, the second clamp regulator generates a second voltage from which the second voltage output level is derived. A passgate multiplexer is coupled to the first and second clamp regulators. The passgate multiplexer receives at least one output voltage select signal. In response to the at least one output voltage select signal the passgate multiplexer selects either the first voltage output level or the second voltage output level.

摘要翻译： 用于在逻辑器件中提供可编程电压输出电平的电路包括用于以第一电压输出电平或第二电压输出电平驱动输出焊盘的上拉器件。 电荷泵产生泵浦电压。 耦合到电荷泵和上拉装置的第一钳位调节器接收第一参考信号。 第一钳位调节器响应于第一参考信号产生第一电压，从该第一电压导出第一电压输出电平。 耦合到上拉装置的第二钳位调节器接收第二参考信号。 响应于第二参考信号，第二钳位调节器产生从其导出第二电压输出电平的第二电压。 通道多路复用器耦合到第一和第二钳位调节器。 所述通道门多路复用器接收至少一个输出电压选择信号。 响应于至少一个输出电压选择信号，通道门复用器选择第一电压输出电平或第二电压输出电平。

公开(公告)号：US06462576B1

公开(公告)日：2002-10-08

申请号：US09661585

申请日：2000-09-14

申请人： Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

发明人： Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

IPC分类号： H03K19177

CPC分类号： H03K19/17728 ,  H03K17/163

摘要： An improved programmable logic device includes a set of I/O cells, a set of logic blocks, and a routing pool that provides connections among the logic blocks and the I/O cells. At least one of the logic blocks includes a programmable logic array that generates product term output signals on product term output lines. A first product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The first product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. Likewise, a second product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The second product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. The logic block further includes first and second output lines and a first programmable switching device that programmably couples the first output line to the output terminal of either the first or the second product term summing circuit. The logic block further includes a second programmable switching device that programmably couples the second output line to the output terminal of either the first or the second product term summing circuit. The programmable logic device has increased functional capacity. In addition, generating an interconnect solution to program the programmable logic device is made simpler by the present invention.

摘要翻译： 改进的可编程逻辑器件包括一组I / O单元，一组逻辑块，以及提供逻辑块和I / O单元之间的连接的路由池。 至少一个逻辑块包括在产品项输出线上产生产品项输出信号的可编程逻辑阵列。 第一乘积项求和电路具有输入端子，其中至少一个耦合到产品项输出线。 第一乘积项求和电路响应于至少一个乘积项输出信号在输出端产生输出信号。 类似地，第二乘积项求和电路具有输入端子，其中至少一个耦合到产品项输出线。 第二乘积项求和电路响应于至少一个乘积项输出信号在输出端产生输出信号。 逻辑块还包括第一和第二输出线以及可编程地将第一输出线耦合到第一或第二乘积项求和电路的输出端的第一可编程开关装置。 逻辑块还包括可编程地将第二输出线耦合到第一或第二乘积项求和电路的输出端的第二可编程开关装置。 可编程逻辑器件具有增加的功能容量。 此外，通过本发明使得生成用于编程可编程逻辑器件的互连解决方案变得更简单。

公开(公告)号：US06278311B1

公开(公告)日：2001-08-21

申请号：US09440207

申请日：1999-11-15

申请人： Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

发明人： Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Rafael C. Camarota

IPC分类号： H03H1126

CPC分类号： H03K19/17728 ,  H03K17/163

摘要： A method for minimizing instantaneous currents ina signal bus is disclosed. The method involves providing a programmable delay element in each of the signal buffers driving the signal on the bus. The programmable delay element in each signal buffer is selectable enabled to include a predetermined time delay. The method involves programming the delay elements in a selected group of the signal buffers t includde the predetermined time delay, so that the selected group of signal buffers each generate an output signal switching after the predetermined delay relative to the switching of output signals generated by other signal buffers.

摘要翻译： 公开了一种使信号总线中的瞬时电流最小化的方法。 该方法涉及在驱动总线上的信号的每个信号缓冲器中提供可编程延迟元件。 每个信号缓冲器中的可编程延迟元件被选择使能以包括预定的时间延迟。 该方法包括对所选择的信号缓冲器组t中的延迟元件进行编程，包括预定的时间延迟，使得所选择的信号缓冲器组在相对于由其他产生的输出信号的切换的预定延迟之后产生切换输出信号 信号缓冲器。

公开(公告)号：US06356107B1

公开(公告)日：2002-03-12

申请号：US09712000

申请日：2000-11-13

申请人： Howard Y. M. Tang ,  Albert Chan ,  Cyrus Y. Tsui ,  Ju Shen

发明人： Howard Y. M. Tang ,  Albert Chan ,  Cyrus Y. Tsui ,  Ju Shen

IPC分类号： G06F738

CPC分类号： H03K19/17772 ,  G01R31/318533 ,  H03K19/17744

摘要： An input/output circuit in an In-system programmable (ISP) logic device allows an output signal from a boundary scan register to be provided as output during programming operations of said ISP logic device. Thus, the ISP logic circuit can provide valid data output to other circuits interfaced to the ISP logic circuit during programming of the ISP logic device, thereby obviating a need to reset the system after reprogramming of the ISP logic device.

摘要翻译： 在系统可编程（ISP）逻辑器件中的输入/输出电路允许在所述ISP逻辑器件的编程操作期间将来自边界扫描寄存器的输出信号提供为输出。 因此，ISP逻辑电路可以在ISP逻辑器件的编程期间向与ISP逻辑电路接口的其它电路提供有效的数据输出，从而避免在对ISP逻辑器件进行重新编程之后复位系统的需要。

公开(公告)号：US6104207A

公开(公告)日：2000-08-15

申请号：US67318

申请日：1998-04-27

申请人： Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui

发明人： Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui

IPC分类号： H03K19/177 ,  G06F7/38 ,  H01L25/00

CPC分类号： H03K19/17772 ,  H03K19/17728 ,  H03K19/17736

摘要： An improved programmable logic device is disclosed. In one embodiment, the programmable logic device includes a plurality of I/O cells and a plurality of logic block clusters. Each logic block cluster has a set of logic blocks and a cluster routing pool, which provides programmable connections among the logic blocks and the I/O cells. A global routing pool provides programmable connections among the logic block clusters and the I/O cells. Each logic block includes a programmable logic array with a plurality of outputs. A product term sharing array in the logic block has a plurality of bus lines, each of which is coupled to at least one of the outputs of the programmable logic array. The product term sharing array also includes a plurality of output lines, each of which is coupled to a plurality of programmable interconnections that each provide a connection to one of the bus lines. Each output line of the product term sharing array is coupled to the same number of programmable interconnections. The logic block also includes a register coupled to at least one of the output lines of the product term sharing array. The register has a data input terminal and a data output terminal. First and second output multiplexers each have a first input terminal coupled to the data input terminal of the register and a second input terminal coupled to the data output terminal of the register.

摘要翻译： 公开了一种改进的可编程逻辑器件。 在一个实施例中，可编程逻辑器件包括多个I / O单元和多个逻辑块簇。 每个逻辑块集群具有一组逻辑块和集群路由池，其提供逻辑块和I / O单元之间的可编程连接。 全局路由池提供逻辑块集群和I / O单元之间的可编程连接。 每个逻辑块包括具有多个输出的可编程逻辑阵列。 逻辑块中的乘积项共享阵列具有多条总线，每条总线耦合到可编程逻辑阵列的至少一个输出。 产品术语共享阵列还包括多个输出线，每个输出线耦合到多个可编程互连，每个可编程互连提供与一条总线线路的连接。 产品术语共享阵列的每个输出线耦合到相同数量的可编程互连。 逻辑块还包括耦合到产品项共享阵列的至少一个输出线的寄存器。 寄存器具有数据输入端子和数据输出端子。 第一和第二输出多路复用器各自具有耦合到寄存器的数据输入端的第一输入端和耦合到寄存器的数据输出端的第二输入端。

公开(公告)号：US06191609B1

公开(公告)日：2001-02-20

申请号：US09433642

申请日：1999-11-03

申请人： Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Allan T. Davidson

发明人： Albert Chan ,  Ju Shen ,  Cyrus Y. Tsui ,  Allan T. Davidson

IPC分类号： H03K19177

CPC分类号： H03K19/1774 ,  G06F1/10

摘要： A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portion of the programmable logic device.

摘要翻译： 可编程逻辑器件包括全局时钟结构和多个局部时钟结构。 每个局部时钟结构将相应的局部时钟信号分配给可编程逻辑器件的对应部分。 全局时钟结构将全局时钟信号分配给可编程逻辑器件的所有部分。

公开(公告)号：US06304099B1

公开(公告)日：2001-10-16

申请号：US09083335

申请日：1998-05-21

申请人： Howard Y. M. Tang ,  Albert Chan ,  Cyrus Y. Tsui ,  Ju Shen

发明人： Howard Y. M. Tang ,  Albert Chan ,  Cyrus Y. Tsui ,  Ju Shen

IPC分类号： G06F738

CPC分类号： H03K19/17772 ,  G01R31/318533 ,  H03K19/17744

摘要： An input/output circuit in an In-system programmable (ISP) logic device allows an output signal from a boundary scan register to be provided as output during programming operations of said ISP logic device. Thus, the ISP logic circuit can provide valid data output to other circuits interfaced to the ISP logic circuit during programming of the ISP logic device, thereby obviating a need to reset the system after reprogramming of the ISP logic device.

摘要翻译： 在系统可编程（ISP）逻辑器件中的输入/输出电路允许在所述ISP逻辑器件的编程操作期间将来自边界扫描寄存器的输出信号提供为输出。 因此，ISP逻辑电路可以在ISP逻辑器件的编程期间向与ISP逻辑电路接口的其它电路提供有效的数据输出，从而避免在对ISP逻辑器件进行重新编程之后复位系统的需要。