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公开(公告)号：US20100048020A1
公开(公告)日：2010-02-25
申请号：US12194526
申请日：2008-08-19
申请人： Alejandro G. Schrott , Eric A. Joseph , Mary Beth Rothwell , Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran , Sarunya Bangsaruntip
发明人： Alejandro G. Schrott , Eric A. Joseph , Mary Beth Rothwell , Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran , Sarunya Bangsaruntip
IPC分类号： H01L21/461
CPC分类号： H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/16 , Y10S438/942 , Y10S977/762 , Y10S977/888 , Y10S977/89 , Y10S977/895
摘要： A process for preparing a phase change memory semiconductor device comprising a (plurality of) nanoscale electrode(s) for alternately switching a chalcogenide phase change material from its high resistance (amorphous) state to its low resistance (crystalline) state, whereby a reduced amount of current is employed, and wherein the plurality of nanoscale electrodes, when present, have substantially the same dimensions.
摘要翻译： 一种制备相变存储器半导体器件的方法，包括用于将硫族化物相变材料从其高电阻（非晶态）状态交替切换到其低电阻（结晶）状态的（多个）纳米级电极，由此减少量 的电流，并且其中当存在时，所述多个纳米级电极具有基本上相同的尺寸。
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公开(公告)号：US20120129313A1
公开(公告)日：2012-05-24
申请号：US13363549
申请日：2012-02-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
IPC分类号： H01L21/62
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.
摘要翻译： 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。
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公开(公告)号：US08536675B2
公开(公告)日：2013-09-17
申请号：US13364153
申请日：2012-02-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.
摘要翻译： 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。
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4.发明授权公开(公告)号：US08138056B2
公开(公告)日：2012-03-20
申请号：US12497596
申请日：2009-07-03
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
IPC分类号： H01L21/20 , H01L21/4763
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.
摘要翻译： 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。
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公开(公告)号：US08466006B2
公开(公告)日：2013-06-18
申请号：US13363549
申请日：2012-02-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.
摘要翻译： 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。
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公开(公告)号：US20120126194A1
公开(公告)日：2012-05-24
申请号：US13364153
申请日：2012-02-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.
摘要翻译： 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。
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公开(公告)号：US20110116307A1
公开(公告)日：2011-05-19
申请号：US12619362
申请日：2009-11-16
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran , Simone Raoux , Alejandro G. Schrott , Daniel Krebs
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran , Simone Raoux , Alejandro G. Schrott , Daniel Krebs
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0069 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A phase change memory cell that includes a bottom electrode, a top electrode separated from the bottom electrode, and growth-dominated phase change material deposited between the bottom electrode and the top electrode and contacting the bottom electrode and the top electrode and surrounded by insulation material at sidewalls thereof. The phase change memory cell in a reset state only includes an amorphous phase of the growth-dominated phase change material within an active volume of the phase change memory cell.
摘要翻译： 一种相变存储单元，包括底部电极，从底部电极分离的顶部电极和沉积在底部电极和顶部电极之间的生长主导的相变材料，并且与底部电极和顶部电极接触并被绝缘材料包围 在其侧壁。 处于复位状态的相变存储单元仅包括在相变存储单元的有效体积内的以生长为主的相变材料的非晶相。
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公开(公告)号：US08233317B2
公开(公告)日：2012-07-31
申请号：US12619362
申请日：2009-11-16
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran , Simone Raoux , Alejandro G. Schrott , Daniel Krebs
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran , Simone Raoux , Alejandro G. Schrott , Daniel Krebs
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0069 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A phase change memory cell that includes a bottom electrode, a top electrode separated from the bottom electrode, and growth-dominated phase change material deposited between the bottom electrode and the top electrode and contacting the bottom electrode and the top electrode and surrounded by insulation material at sidewalls thereof. The phase change memory cell in a reset state only includes an amorphous phase of the growth-dominated phase change material within an active volume of the phase change memory cell.
摘要翻译： 一种相变存储单元，包括底部电极，从底部电极分离的顶部电极和沉积在底部电极和顶部电极之间的生长主导的相变材料，并且与底部电极和顶部电极接触并被绝缘材料包围 在其侧壁。 处于复位状态的相变存储单元仅包括在相变存储单元的有效体积内的以生长为主的相变材料的非晶相。
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公开(公告)号：US20090268507A1
公开(公告)日：2009-10-29
申请号：US12111258
申请日：2008-04-29
申请人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
CPC分类号： H01L45/144 , G11C13/0004 , H01L45/06 , H01L45/1233 , H01L45/1253 , Y10T29/49002
摘要： A phase change memory control ring lower electrode is disclosed. The lower electrode includes an outer ring electrode in thermal contact with a phase change memory element, an inner seed layer disposed within the outer ring electrode and in contact with the phase change memory element, and an electrically conductive bottom layer coupled to the outer ring electrode.
摘要翻译： 公开了一种相变存储器控制环下电极。 下电极包括与相变存储元件热接触的外环电极，设置在外环电极内并与相变存储元件接触的内种子层，以及耦合到外环电极的导电底层 。
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公开(公告)号：US07868313B2
公开(公告)日：2011-01-11
申请号：US12111258
申请日：2008-04-29
申请人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
IPC分类号： H01L21/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L45/06 , H01L45/1233 , H01L45/1253 , Y10T29/49002
摘要： A phase change memory control ring lower electrode is disclosed. The lower electrode includes an outer ring electrode in thermal contact with a phase change memory element, an inner seed layer disposed within the outer ring electrode and in contact with the phase change memory element, and an electrically conductive bottom layer coupled to the outer ring electrode.
摘要翻译： 公开了一种相变存储器控制环下电极。 下电极包括与相变存储元件热接触的外环电极，设置在外环电极内并与相变存储元件接触的内种子层，以及耦合到外环电极的导电底层 。
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