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公开(公告)号：US07593358B2
公开(公告)日：2009-09-22
申请号：US11067461
申请日：2005-02-25
摘要： Transmitter device including a modulator apparatus for the generation of a modulated digital signal in a remote control system. The modulated signal is defined by at least one characteristic quantity correlated to an information to transmit. The modulator apparatus is characterized by including a finite states machine for generating a modulating digital signal to combine with a carrier signal and obtain the modulated signal. The finite states machine generates the modulating signal on the basis of digital data corresponding to said at least one characteristic quantity.
摘要翻译： 发射机装置包括用于在遥控系统中产生调制数字信号的调制器装置。 调制信号由与要发送的信息相关联的至少一个特征量定义。 调制器装置的特征在于包括一个有限状态机，用于产生调制数字信号以与载波信号组合并获得调制信号。 有限状态机根据对应于所述至少一个特征量的数字数据产生调制信号。
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公开(公告)号：US20050201756A1
公开(公告)日：2005-09-15
申请号：US11067461
申请日：2005-02-25
摘要： Transmitter device including a modulator apparatus for the generation of a modulated digital signal in a remote control system. The modulated signal is defined by at least one characteristic quantity correlated to an information to transmit. The modulator apparatus is characterized by including a finite states machine for generating a modulating digital signal to combine with a carrier signal and obtain the modulated signal. The finite states machine generates the modulating signal on the basis of digital data corresponding to said at least one characteristic quantity.
摘要翻译： 发射机装置包括用于在遥控系统中产生调制数字信号的调制器装置。 调制信号由与要发送的信息相关联的至少一个特征量定义。 调制器装置的特征在于包括一个有限状态机，用于产生调制数字信号以与载波信号组合并获得调制信号。 有限状态机根据对应于所述至少一个特征量的数字数据产生调制信号。
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3.发明申请A LOW AREA ARCHITECTURE SOLUTION FOR EMBEDDED FLASH PROGRAMMING MEMORIES IN MICROCONTROLLERS 审中-公开用于微控制器中嵌入式闪存编程存储器的低面积架构解决方案公开(公告)号：US20060271728A1
公开(公告)日：2006-11-30
申请号：US11420846
申请日：2006-05-30
IPC分类号： G06F12/00
CPC分类号： G06F9/4403 , G06F8/60
摘要： A low area architecture for embedded programming flash memory portions in microcontrollers is based on substitution of the ROM/RAM/CORE functionality with a digital ISP controller implemented in a finite state machine and a standard interface. After connecting ports of the embedded programming flash memory portion and releasing a RESET pin, the microcontroller enters a particular operating mode and is managed by the digital ISP controller instead of the CORE. The ROM is not required to set up the microcontroller, and as a consequence, transfer of the boot program from the ROM to the RAM is not requested for subsequent execution.
摘要翻译： 用于微控制器中嵌入式编程闪存部分的低面积架构是基于在有限状态机和标准接口中实现的数字ISP控制器代替ROM / RAM / CORE功能。 在连接嵌入式编程闪存部分的端口并释放RESET引脚后，微控制器进入特定的工作模式，由数字ISP控制器代替CORE进行管理。 ROM不需要设置微控制器，因此，引导程序从ROM传输到RAM不被要求后续执行。
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4.发明授权Process for managing system stacks in microcontrollers, corresponding device and computer program product 有权用于管理微控制器，相应设备和计算机程序产品中的系统堆栈的过程公开(公告)号：US07219196B2
公开(公告)日：2007-05-15
申请号：US10623146
申请日：2003-07-17
申请人： Santi Carlo Adamo , Edmondo Gangi
发明人： Santi Carlo Adamo , Edmondo Gangi
CPC分类号： G06F9/30163
摘要： In order to manage, in the interrupt stage, a memory stack associated with a microcontroller according to a Program Counter signal and to a Condition Code Register signal that can be contained in respective registers, a first part of memory stack is provided which comprises a register for the Program Counter signal, and a second part of memory stack consisting of a bank of memory elements equal in number to the number of bits of the Condition Code Register signal for the number of the interrupts of the microcontroller. The two parts of stack are made to function in parallel by respective stack-pointer signals.
摘要翻译： 为了在中断阶段中根据程序计数器信号管理与微控制器相关联的存储器堆栈以及可以包含在相应寄存器中的条件码寄存器信号，提供存储器堆栈的第一部分，其包括寄存器 用于程序计数器信号的存储器堆栈，以及存储器堆栈的第二部分，其由与微控制器的中断数量的条件码寄存器信号的位数相等的一组存储器元件组成。 堆叠的两个部分通过相应的堆栈指针信号并行起作用。
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公开(公告)号：US06862584B2
公开(公告)日：2005-03-01
申请号：US09727297
申请日：2000-11-29
IPC分类号： G06F7/544 , G06F15/18 , G06G7/00 , G06N5/04 , H03K20060101
CPC分类号： G06N5/048 , G06F7/544 , Y10S706/908 , Y10S706/916
摘要： The calculation circuit comprises a subtracter having a first and a second input receiving a first and, respectively, a second input datum; a first output supplying a first output datum equal to the difference between the first and the second input datum; and a second output supplying a sign flag indicating the sign of the first output datum; an XOR logic gate having a first input receiving the sign flag, a second input receiving a first logic selection signal assuming a first level for the selection of the logical fuzzy union operation and a second level for the selection of the logical fuzzy intersection operation, and an output supplying a second logic selection signal; and a multiplexer having a first and a second datum input receiving the first and, respectively, the second input datum; a selection input receiving the second selection signal; and an output supplying a second output datum constituted by the first or the second input datum (A, B) as a function of the level assumed by the second selection signal.
摘要翻译： 计算电路包括具有第一和第二输入的减法器，该第一和第二输入接收第一和第二输入数据; 提供等于第一和第二输入数据之间的差的第一输出数据的第一输出; 以及第二输出，提供指示所述第一输出数据的符号的符号标志; XOR逻辑门，具有接收符号标志的第一输入端，接收第一逻辑选择信号的第二输入端，所述第一逻辑选择信号假定用于选择逻辑模糊联合运算的第一级别和用于选择逻辑模糊交会操作的第二级别;以及 输出提供第二逻辑选择信号; 以及多路复用器，其具有接收第一和第二输入数据的第一和第二数据输入; 接收第二选择信号的选择输入; 以及作为由第二选择信号假设的电平的函数，提供由第一或第二输入数据（A，B）构成的第二输出数据的输出。
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