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1.发明申请Method and BIST architecture for fast memory testing in platform-based integrated circuit 有权方法和BIST架构，用于基于平台的集成电路中的快速内存测试公开(公告)号：US20060156088A1
公开(公告)日：2006-07-13
申请号：US10999493
申请日：2004-11-30
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C29/26 , G11C2029/2602
摘要： The present invention provides a method and BIST architecture for fast memory testing in a platform-based integrated circuit. The method may include steps as follows. An Mem-BIST controller transmitter is started to generate input signals for a memory in a platform using a deterministic and unconditional test algorithm. The input signals are delayed by a first group of pipelines by n clock cycles. The delayed input signals are received by the memory and an output signal is generated by the memory. The output signal is delayed by a second pipeline by m clock cycles. An Mem-BIST controller receiver is started to receive the delayed output signal for comparison.
摘要翻译： 本发明提供了一种用于基于平台的集成电路中的快速存储器测试的方法和BIST架构。 该方法可以包括以下步骤。 启动Mem-BIST控制器发送器，使用确定性和无条件测试算法为平台中的存储器生成输入信号。 输入信号被第一组管道延迟了n个时钟周期。 延迟的输入信号由存储器接收，并且由存储器产生输出信号。 输出信号被第二个流水线延迟了m个时钟周期。 启动Mem-BIST控制器接收器以接收延迟的输出信号进行比较。
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公开(公告)号：US20070143648A1
公开(公告)日：2007-06-21
申请号：US11311388
申请日：2005-12-19
IPC分类号： G11C29/00
CPC分类号： G11C5/04
摘要： A memory timing model is provided, which includes an address input, a multiple-bit data input, a multiple-bit data output, a capacity C and a width N. N one-bit wide memory modules are instantiated in parallel with one another between respective bits of the data input and the data output. Each memory module has a capacity of C bits addressed by the address input.
摘要翻译： 提供了存储器定时模型，其包括地址输入，多位数据输入，多位数据输出，容量C和宽度N.N个1位宽存储器模块彼此并行地实例化 数据输入的各个位和数据输出。 每个存储器模块具有通过地址输入寻址的C位的容量。
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公开(公告)号：US06587990B1
公开(公告)日：2003-07-01
申请号：US09678201
申请日：2000-10-01
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： The present invention is a method and apparatus for optimizing the design of a combinational circuit. The method includes constructing a circuit sheaf for the combinational circuit and then performing vector optimization with domination. In the preferred embodiment, a complete BDD B is determined and, from that, a list of F-sets is computed. If the combinational circuit includes cells other than NOT, AND and XOR cells, the circuit is first transformed such that it only has those types of cells.
摘要翻译： 本发明是一种优化组合电路设计的方法和装置。 该方法包括为组合电路构建电路束，然后进行矢量优化。 在优选实施例中，确定完整的BDD B，并且从中计算出F组的列表。 如果组合电路包括除NOT，AND和XOR单元以外的单元，则首先对电路进行转换，使其仅具有这些类型的单元。
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公开(公告)号：US07818703B2
公开(公告)日：2010-10-19
申请号：US11757200
申请日：2007-06-01
申请人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
发明人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to locally place each selected cell within the module layout so that each cell pin of the selected cells and each port of the module layout occupies a unique vertical routing track within the module layout.
摘要翻译： 用于在集成电路布局图案中布局模块的系统具有单元库和单元布置系统。 细胞库包括多个细胞。 单元布置系统适于从单元库中选择一个或多个单元，并将每个选定单元局部放置在模块布局内，使得所选单元格的每个单元管脚和模块布局的每个端口都占用一个唯一的垂直布线轨道 模块布局。
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公开(公告)号：US20080016482A1
公开(公告)日：2008-01-17
申请号：US11757200
申请日：2007-06-01
申请人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
发明人： Alexander Andreev , Ivan Pavisic , Anatoli Bolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to locally place each selected cell within the module layout so that each cell pin of the selected cells and each port of the module layout occupies a unique vertical routing track within the module layout.
摘要翻译： 用于在集成电路布局图案中布局模块的系统具有单元库和单元布置系统。 细胞库包括多个细胞。 单元布置系统适于从单元库中选择一个或多个单元，并将每个选定单元局部放置在模块布局内，使得所选单元格的每个单元管脚和模块布局的每个端口都占用一个唯一的垂直布线轨道 模块布局。
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公开(公告)号：US20060161803A1
公开(公告)日：2006-07-20
申请号：US11038698
申请日：2005-01-20
IPC分类号： G06F11/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/72
摘要： The present invention provides a memory BISR architecture for a slice. The architecture includes (1) a plurality of physical memory instances; (2) a Mem_BIST controller, communicatively coupled to the plurality of physical memory instances, for testing the plurality of physical memory instances; (3) a FLARE module, communicatively coupled to the Mem_BIST controller, including a scan chain of registers for storing test results of the plurality of physical memory instances, each of the plurality of physical memory instances M_i being assigned one FLARE bit f_i, i=1, 2, . . . , n, the FLARE module being used by the Mem_BIST controller to scan in an error vector F=(f—1, f—2, . . . , f_n); (4) a BISR controller, communicatively coupled to the FLARE module, a ROM module and a REPAIR_CONFIGURATION module, for scanning out the error vector F from the FLARE module to computer a repair configuration vector R=(r—1, r—2, . . . , r_n); and (5) a FUSE module, communicatively coupled to the BISR controller and the REPAIR_CONFIGURATION module, for storing the repair configuration vector R. The REPAIR_CONFIGURATION module, communicatively coupled to the plurality of physical memory instances M_i and an integrated circuit design D, includes switch module instances S for switching among the plurality of physical memory instances in accordance with the repair configuration vector R. The ROM module stores a vector U indicating usage of the plurality of physical memory instances M_i by the integrated circuit design D.
摘要翻译： 本发明提供了一种用于切片的存储器BISR架构。 该架构包括（1）多个物理存储器实例; （2）通信地耦合到所述多个物理存储器实例的用于测试所述多个物理存储器实例的Mem_BIST控制器; （3）FLARE模块，通信地耦合到所述Mem_BIST控制器，包括用于存储所述多个物理存储器实例的测试结果的寄存器扫描链，所述多个物理存储器实例M_i中的每一个被分配一个FLARE位f_i，i = 1，2，... 。 。 ，n，由Mem_BIST控制器使用的FLARE模块以错误向量F =（f 1 - 1，f 2 - ，...，f_n）进行扫描; （4）通信地耦合到FLARE模块的BISR控制器，ROM模块和REPAIR_CONFIGURATION模块，用于从FLARE模块向计算机扫描出错误向量F，修复配置向量R =（r - > 1，r 2，...，r_n）; 和（5）通信地耦合到BISR控制器和REPAIR_CONFIGURATION模块的FUSE模块，用于存储修复配置向量R.通信地耦合到多个物理存储器实例M_i和集成电路设计D的REPAIR_CONFIGURATION模块包括开关 模块实例S，用于根据修复配置向量R在多个物理存储器实例之间切换.ROM模块通过集成电路设计D存储指示多个物理存储器实例M_i的使用的向量U。
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公开(公告)号：US20050050426A1
公开(公告)日：2005-03-03
申请号：US10648038
申请日：2003-08-26
CPC分类号： H03M13/2771 , H03M13/2764 , H03M13/2957
摘要： A routing multiplexer system provide p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.
摘要翻译： 路由多路复用器系统基于所选择的p个输入的排列来提供p个输出。 多个模块中的每一个具有两个输入，两个输出和一个控制输入，并且被布置为基于控制输入处的位的值，以直接或转置的顺序将两个输入端的信号提供给两个输出。 模块的第一个p / 2组耦合到n个输入端，第二个p / 2组模块提供n个输出。 多个控制位表各自包含基于相应置换的布置中的多个位。 存储器响应于所选择的置换，以基于相应控制位表的相应位值向相应模块提供位，由此建立对输出的输入的选择和可编程排列。
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公开(公告)号：US06536016B1
公开(公告)日：2003-03-18
申请号：US09626037
申请日：2000-07-27
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： Constant pins are determined in a combinational circuit by associating an input of a combinational circuit with a first variable and a second variable, with the second variable being the complement of the first variable. For a first logical cell interconnected to such input, a first mathematical representation and a second mathematical representation are computed. The first mathematical representation is a function of the operation of the first logical cell and a function of the first variable, and the second mathematical representation is a function of the operation of the first logical cell and a function of the second variable. A determination is then made as to whether one of the first and second mathematical representations is equal to a constant.
摘要翻译： 在组合电路中通过将组合电路的输入与第一变量和第二变量相关联来确定恒定引脚，第二变量是第一变量的补码。 对于与这种输入互连的第一逻辑单元，计算第一数学表示和第二数学表示。 第一数学表示是第一逻辑单元的操作和第一变量的函数的函数，第二数学表示是第一逻辑单元的操作和第二变量的函数的函数。 然后确定第一和第二数学表示中的一个是否等于常数。
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9.发明授权公开(公告)号：US06530063B1
公开(公告)日：2003-03-04
申请号：US09677276
申请日：2000-10-02
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： The present invention involves a method for determining constant pins in a combinational circuit. The method comprises the steps of associating an input of a combinational circuit with a first variable and a second variable, wherein said second variable is the compliment of said first variable, computing for a first logical cell interconnected to said input a first canonical representation, wherein said first canonical representation is a function of the operation of said first logical cell and a function of said first value, computing for said first logical cell a second canonical representation, wherein said second canonical representation is a function of the operation of said first logical cell and a function of said second value, determining whether one of said first and second canonical representations is equal to zero.
摘要翻译： 本发明涉及一种用于确定组合电路中恒定引脚的方法。 该方法包括以下步骤：将组合电路的输入与第一变量和第二变量相关联，其中所述第二变量是所述第一变量的补码，对于与所述输入互连的第一逻辑单元计算第一规范表示，其中 所述第一规范表示是所述第一逻辑单元的操作和所述第一值的函数的函数，对于所述第一逻辑单元计算第二规范表示，其中所述第二规范表示是所述第一逻辑单元的操作的函数 以及所述第二值的函数，确定所述第一和第二规范表示中的一个是否等于零。
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公开(公告)号：US20080049719A1
公开(公告)日：2008-02-28
申请号：US11924385
申请日：2007-10-25
IPC分类号： H04L13/00
CPC分类号： H03M13/2771 , H03M13/2764 , H03M13/2957
摘要： A routing multiplexer system provides p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.
摘要翻译： 路由复用器系统基于所选择的p个输入的排列来提供p个输出。 多个模块中的每一个具有两个输入，两个输出和一个控制输入，并且被布置为基于控制输入端的位的值，以直接或转置的顺序向两个输出提供两个输入端的信号。 模块的第一个p / 2组耦合到n个输入端，第二个p / 2组模块提供n个输出。 多个控制位表各自包含基于相应置换的布置中的多个位。 存储器响应于所选择的置换，以基于相应控制位表的相应位值向相应模块提供位，由此建立对输出的输入的选择和可编程排列。
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