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1.发明授权Data processor and method for providing show cycles on a fast multiplexed bus 失效用于在快速复用总线上提供显示周期的数据处理器和方法
公开(公告)号：US5548794A
公开(公告)日：1996-08-20
申请号：US349286
申请日：1994-12-05
CPC分类号： G06F11/3656
摘要： A data processor (10) and method which provides show-cycles on a fast multiplexed bus (28) using two distinct modes of operation. A first mode of operation supports a standard show-cycle on a multiplexed bus for interface to a passive device such as a logic analyzer (100). A second mode of operation supports emulation tools (100) with real-time tracking of control functions using a multiplexed bus. During each of the modes of operation of the data processor (10), both read and write show cycles are supported and are consistently provided in a similar format.
摘要翻译： 一种使用两种不同操作模式在快速复用总线（28）上提供显示周期的数据处理器（10）和方法。 第一操作模式支持多路复用总线上的标准显示循环，用于与诸如逻辑分析器（100）的无源设备的接口。 第二种操作模式支持使用多路复用总线实时跟踪控制功能的仿真工具（100）。 在数据处理器（10）的每种操作模式期间，支持读和写显示周期，并以类似的格式一致地提供。
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2.发明授权Integrated circuit data processor which provides external sensibility of internal signals during reset 失效集成电路数据处理器，在复位期间提供内部信号的外部灵敏度
公开(公告)号：US5574894A
公开(公告)日：1996-11-12
申请号：US333658
申请日：1994-11-03
CPC分类号： G06F11/3632 , G06F11/3648
摘要： An integrated circuit terminal of a data processing system (10) is used to communicate multiplexed signals with an external device. During a reset operation in which a reset signal is asserted, a desired internal clock signal is driven to the integrated circuit terminal such that an emulation system (52) may use the internal clock signal to synchronize an emulation operation. After the reset signal is negated, the emulation system synthesizes the internal clock signal for use during emulation. External visibility of a write operation to a register which controls pertinent signal parameters is provided via other integrated circuit terminals when the data processor operates in an emulation mode. The external visibility allows the development system to make similar changes to corresponding signal parameters therein. Therefore, the development system is able to accurately synchronize an emulation operation even when signal parameters are modified during operation.
摘要翻译： 数据处理系统（10）的集成电路终端用于与外部设备通信多路复用信号。 在其中确定复位信号的复位操作期间，期望的内部时钟信号被驱动到集成电路端子，使得仿真系统（52）可以使用内部时钟信号来同步仿真操作。 在复位信号被否定之后，仿真系统合成内部时钟信号，以便在仿真期间使用。 当数据处理器以仿真模式运行时，通过其他集成电路终端提供对控制相关信号参数的寄存器的写入操作的外部可视性。 外部可视性允许开发系统对其中的相应信号参数进行类似的改变。 因此，即使在操作期间修改信号参数时，开发系统也能够精确地同步仿真操作。
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3.发明授权Method and system including memory patching utilizing a transmission control signal and circuit 失效方法和系统包括利用传输控制信号和电路的存储器补丁
公开(公告)号：US5813043A
公开(公告)日：1998-09-22
申请号：US678898
申请日：1996-07-12
摘要： A data processing system (100, 300) allows an individually mappable word of memory to patch a desired memory location. During operation, a memory system (130) monitors an address/control bus to determine when an access to a specified word in a system memory (120) occurs. When an access to the specified word occurs, address comparators (140) determine if a memory location to be patched is being accessed, and provides an active signal to the access control circuit (150), which prevents data flow with the system memory (120) and enables the data flow with a separate memory (170) by controlling a transmission gate 115. Therefore, the data access occurs from the separate memory and not the system memory.
摘要翻译： 数据处理系统（100,300）允许单独可映射的存储器字来修补期望的存储器位置。 在操作期间，存储器系统（130）监视地址/控制总线以确定何时发生对系统存储器（120）中的指定字的访问。 当访问指定的字时，地址比较器（140）确定是否正在访问要修补的存储器位置，并且向访问控制电路（150）提供有效信号，这阻止了与系统存储器（120）的数据流 ），并且通过控制传输门115使得能够利用单独的存储器（170）进行数据流。因此，数据访问从分离的存储器而不是系统存储器进行。
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