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公开(公告)号：US5748490A
公开(公告)日：1998-05-05
申请号：US548929
申请日：1995-10-26
申请人： J. Greg Viot , Oded Yishay
发明人： J. Greg Viot , Oded Yishay
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： A process (601-611) and implementing computer system (13) for selecting a specific logic circuit among a group of otherwise acceptable alternative circuits, as represented by prime implicant terms (607), includes determining and assigning a power consumption factor (609) to each of the alternative logic circuit implementations. In the disclosed example, the probability of switching logic states (313, 513) is determined and used as a measure of the power consumption factor associated with each of the acceptable and valid prime implicant solutions for a given logic function. From a group of acceptable prime implicant solutions, the power optimum solution is chosen (611) which has been determined to be the most likely to consume the least amount of power in implementing the desired logic function.
摘要翻译： 一种用于选择由主要含义项（607）表示的一组否则可接受的替代电路中的特定逻辑电路的处理（601-611）和实现计算机系统（13），包括确定和分配功耗因数（609） 到每个替代逻辑电路实现。 在所公开的示例中，确定切换逻辑状态（313,513）的概率，并将其用作与给定逻辑功能的每个可接受和有效的初始含义解相关联的功耗因数的度量。 从一组可接受的主要牵连解决方案中，选择功率最优解（611），其被确定为在实现期望的逻辑功能中消耗最少功率的最有可能性。
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2.发明授权Data processor and method for providing show cycles on a fast multiplexed bus 失效用于在快速复用总线上提供显示周期的数据处理器和方法
公开(公告)号：US5548794A
公开(公告)日：1996-08-20
申请号：US349286
申请日：1994-12-05
CPC分类号： G06F11/3656
摘要： A data processor (10) and method which provides show-cycles on a fast multiplexed bus (28) using two distinct modes of operation. A first mode of operation supports a standard show-cycle on a multiplexed bus for interface to a passive device such as a logic analyzer (100). A second mode of operation supports emulation tools (100) with real-time tracking of control functions using a multiplexed bus. During each of the modes of operation of the data processor (10), both read and write show cycles are supported and are consistently provided in a similar format.
摘要翻译： 一种使用两种不同操作模式在快速复用总线（28）上提供显示周期的数据处理器（10）和方法。 第一操作模式支持多路复用总线上的标准显示循环，用于与诸如逻辑分析器（100）的无源设备的接口。 第二种操作模式支持使用多路复用总线实时跟踪控制功能的仿真工具（100）。 在数据处理器（10）的每种操作模式期间，支持读和写显示周期，并以类似的格式一致地提供。
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公开(公告)号：US5717851A
公开(公告)日：1998-02-10
申请号：US290667
申请日：1994-08-15
申请人： Oded Yishay , Joseph Jelemensky
发明人： Oded Yishay , Joseph Jelemensky
CPC分类号： G06F11/3648
摘要： Existing chip select comparator logic (42) is used to compare a portion of the address value with a range of chip select addresses to provide a match signal for use by both the chip select logic (70) and a breakpoint logic circuit (50.x). The match signal is generated by the chip select logic circuit and is reused by the breakpoint logic circuit to perform a different and distinct function. By using the match signal and a breakpoint enable bit, the breakpoint logic circuit selectively asserts a breakpoint signal. Subsequently, a central processing unit (12) receives the breakpoint signal and initiates a breakpoint exception operation to determine whether the breakpoint condition is met and whether further action should be taken.
摘要翻译： 现有的芯片选择比较器逻辑（42）用于将地址值的一部分与芯片选择地址的范围进行比较，以提供匹配信号供芯片选择逻辑（70）和断点逻辑电路（50.x）使用 ）。 匹配信号由芯片选择逻辑电路产生，并由断点逻辑电路重新使用以执行不同且不同的功能。 通过使用匹配信号和断点使能位，断点逻辑电路选择性地断言断点信号。 随后，中央处理单元（12）接收断点信号并启动断点异常操作，以确定是否满足断点条件以及是否应采取进一步措施。
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公开(公告)号：US5623687A
公开(公告)日：1997-04-22
申请号：US494664
申请日：1995-06-26
IPC分类号： G06F9/445 , G06F15/177 , G06F13/00
CPC分类号： G06F1/24 , G06F15/177 , G06F9/4411 , Y10S707/99931
摘要： Data processor (10) configures internal circuitry during execution of a reset operation in response a logic state of a Mode Select signal. If an external bus control (44) determines the Mode Select signal is in a first logic state, configuration data is provided from a mask register (40). The data is transferred to a plurality of configuration registers (50) and, subsequently, to a remaining portion of data processor (10). If the Mode Select signal is in a second logic state, configuration data is provided from a plurality of bus terminals (48). The data is transferred to the plurality of configuration registers (50). The contents of the plurality of configuration registers (50) are transferred to bus interface unit (42) which subsequently transfers the data to a remaining portion of data processor (10).
摘要翻译： 响应于模式选择信号的逻辑状态，数据处理器（10）在执行复位操作期间配置内部电路。 如果外部总线控制（44）确定模式选择信号处于第一逻辑状态，则从掩码寄存器（40）提供配置数据。 数据被传送到多个配置寄存器（50），随后被传送到数据处理器（10）的剩余部分。 如果模式选择信号处于第二逻辑状态，则从多个总线端子（48）提供配置数据。 数据被传送到多个配置寄存器（50）。 多个配置寄存器（50）的内容被传送到总线接口单元（42），随后将数据传送到数据处理器（10）的剩余部分。
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5.发明授权Method and apparatus in a data processing system for selectively inserting bus cycle idle time 失效用于选择性地插入总线周期空闲时间的数据处理系统中的方法和装置
公开(公告)号：US5664168A
公开(公告)日：1997-09-02
申请号：US600144
申请日：1996-02-12
申请人： Oded Yishay , Ann E. Harwood , Chinh H. Le
发明人： Oded Yishay , Ann E. Harwood , Chinh H. Le
IPC分类号： G06F13/376 , G06F13/42 , G06F13/10
CPC分类号： G06F13/4217 , G06F13/376
摘要： Method and apparatus in a data processing system (10) for selectively inserting bus cycle idle time. The present invention allows a data processing system (10) to selectively insert a predetermined number of idle clocks at the end of a bus cycle. In one embodiment of the present invention, there is a base register (48) and an option register (46) corresponding to each one of the chip select terminals (73). In one embodiment of the present invention, each option register (46) includes a user programmable idle control bit (110). If a first chip select is used to select a peripheral device during a bus cycle to that same peripheral device, the idle control bit (110) which corresponds to the first chip select determines whether or not one or more idle clocks will be inserted after that bus cycle.
摘要翻译： 用于选择性地插入总线周期空闲时间的数据处理系统（10）中的方法和装置。 本发明允许数据处理系统（10）在总线周期结束时选择性地插入预定数量的空闲时钟。 在本发明的一个实施例中，存在与芯片选择端子（73）中的每一个相对应的基址寄存器（48）和选项寄存器（46）。 在本发明的一个实施例中，每个选项寄存器（46）包括用户可编程的空闲控制位（110）。 如果第一芯片选择用于在到同一外围设备的总线周期期间选择外围设备，则与第一芯片选择相对应的空闲控制位（110）确定在此之后是否插入一个或多个空闲时钟 公交车周期。
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6.发明授权Method and apparatus for scan testing an array in a data processing system 失效用于在数据处理系统中扫描测试阵列的方法和装置
公开(公告)号：US5414714A
公开(公告)日：1995-05-09
申请号：US857878
申请日：1992-03-26
IPC分类号： G01R31/317 , G11C29/32 , G01R31/28 , G06F11/00
CPC分类号： G01R31/317 , G11C29/32
摘要： A method and apparatus for scan testing an array (20) in a data processing system (10). In one form, the present invention uses a scanning sense amplifier (22x) which can perform the three functions of a sense amplifier, a master test latch for scan testing, and a slave test latch for scan testing. Using one scanning sense amplifier (22x) to perform all three functions reduces the amount of circuitry required to scan test an array (20). The same stimulus is applied twice to the array (20); and half of the output data bits are scanned out during each application of the stimulus. One extra output data bit is also scanned out during each application of the stimulus. The end result is a reduction in the circuitry required to perform scan testing.
摘要翻译： 一种用于扫描测试数据处理系统（10）中的阵列（20）的方法和装置。 在一种形式中，本发明使用可执行读出放大器，用于扫描测试的主测试锁存器和用于扫描测试的从测试锁存器的三个功能的扫描读出放大器（22x）。 使用一个扫描读出放大器（22x）执行所有三个功能可以减少扫描测试阵列（20）所需的电路数量。 对阵列（20）施加相同的刺激两次; 并且在每次应用刺激期间扫描输出数据位的一半。 每次应用刺激时，也会扫描一个额外的输出数据位。 最终的结果是减少执行扫描测试所需的电路。
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公开(公告)号：US09087003B2
公开(公告)日：2015-07-21
申请号：US13666289
申请日：2012-11-01
申请人： Leo G. Dehner , Oded Yishay
发明人： Leo G. Dehner , Oded Yishay
CPC分类号： G06F17/142 , G06F1/0328 , G06F17/14
摘要： A method and apparatus may be used to generate complex exponentials for either frequency domain or time domain applications by programming input parameter values into a complex exponential vector generator (260) having a frequency generator stage (281) and a vector phase accumulator stage (282) arranged with a vector element multiplier stage (283) to generate complex exponential phase index values (α0, α1, . . . αv−1) that are processed by a complex exponential generator stage (284) to output a plurality of complex exponential values (e.g., ej2πα0, ej2πα1, . . . ej2παv−1) that may be rearranged by a permutation unit (286) for use by vector data path.
摘要翻译： 方法和装置可以用于通过将输入参数值编程到具有频率发生器级（281）和矢量相位累加器级（282）的复指数矢量生成器（260）中来为频域或时域应用产生复指数， 布置有矢量元素乘法器级（283）以产生由复指数发生器级（284）处理的复数指数相位索引值（α0，α1，...αv-1），以输出多个复指数值 例如ej2＆pgr;α0，ej2＆pgr;α1，... ej2＆pgr;αv-1），其可以由置换单元（286）重新排列以供矢量数据路径使用。
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8.发明授权
公开(公告)号：US5704039A
公开(公告)日：1997-12-30
申请号：US632179
申请日：1996-04-15
CPC分类号： G06F12/1466 , G11C7/24 , G11C8/20
摘要： A data processing system (10) allows an authorized user to unlock a security mode by providing a code stored in a plurality of mask registers (60,62,66) such that the system is selectively allowed to communicate with an external device. When an reset signal is received, a selector (48) selects a first mask register (60) and retrieves a first stored address value and a first stored data value therefrom. The first stored address and data values are respectively compared with a first address value and a first data value by a comparator (44). This process of selecting and comparing continues until a final match signal is asserted. When the final match signal is asserted, a secure signal is negated and the system may communicate with the external user.
摘要翻译： 数据处理系统（10）允许授权用户通过提供存储在多个屏蔽寄存器（60,62,66）中的代码来解锁安全模式，使得系统被选择性地允许与外部设备通信。 当接收到复位信号时，选择器（48）选择第一屏蔽寄存器（60）并且从中检索第一存储的地址值和第一存储的数据值。 第一存储的地址和数据值分别通过比较器（44）与第一地址值和第一数据值进行比较。 该选择和比较的过程继续进行，直到最终匹配信号被断言为止。 当最终匹配信号被断言时，安全信号被否定，并且系统可以与外部用户通信。
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9.发明授权Integrated circuit data processor which provides external sensibility of internal signals during reset 失效集成电路数据处理器，在复位期间提供内部信号的外部灵敏度
公开(公告)号：US5574894A
公开(公告)日：1996-11-12
申请号：US333658
申请日：1994-11-03
CPC分类号： G06F11/3632 , G06F11/3648
摘要： An integrated circuit terminal of a data processing system (10) is used to communicate multiplexed signals with an external device. During a reset operation in which a reset signal is asserted, a desired internal clock signal is driven to the integrated circuit terminal such that an emulation system (52) may use the internal clock signal to synchronize an emulation operation. After the reset signal is negated, the emulation system synthesizes the internal clock signal for use during emulation. External visibility of a write operation to a register which controls pertinent signal parameters is provided via other integrated circuit terminals when the data processor operates in an emulation mode. The external visibility allows the development system to make similar changes to corresponding signal parameters therein. Therefore, the development system is able to accurately synchronize an emulation operation even when signal parameters are modified during operation.
摘要翻译： 数据处理系统（10）的集成电路终端用于与外部设备通信多路复用信号。 在其中确定复位信号的复位操作期间，期望的内部时钟信号被驱动到集成电路端子，使得仿真系统（52）可以使用内部时钟信号来同步仿真操作。 在复位信号被否定之后，仿真系统合成内部时钟信号，以便在仿真期间使用。 当数据处理器以仿真模式运行时，通过其他集成电路终端提供对控制相关信号参数的寄存器的写入操作的外部可视性。 外部可视性允许开发系统对其中的相应信号参数进行类似的改变。 因此，即使在操作期间修改信号参数时，开发系统也能够精确地同步仿真操作。
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10.发明授权Method and apparatus for performing read accesses from a counter which avoid large rollover error when multiple read access cycles are used 失效用于从计数器执行读取访问的方法和装置，其在使用多个读取访问周期时避免大的翻转错误
公开(公告)号：US5566322A
公开(公告)日：1996-10-15
申请号：US154774
申请日：1993-11-19
摘要： Method and apparatus for performing read accesses from a counter (40) while avoiding the large rollover error that may occur when the counter (40) is read using more than one read access cycle. In one embodiment, the present invention monitors the most significant bit of the lower portion (44) of counter (40) for a transition indicating that a rollover has taken place. If a rollover has not occurred, read accesses take place in the normal manner. However, if a rollover has occurred during the latency period between a read access from the upper portion (42) of counter (40) and a corresponding read access from the lower portion (44) of counter (40), the read access from the lower portion (44) is inhibited and a default value is placed on the bus (36) instead.
摘要翻译： 用于从计数器（40）执行读取访问的方法和装置，同时避免当使用多于一个读取访问周期读取计数器（40）时可能发生的大的翻转错误。 在一个实施例中，本发明监视计数器（40）的下部（44）的最高有效位，用于指示已经发生翻转。 如果没有发生翻转，则读取访问以正常方式进行。 然而，如果在来自计数器（40）的上部（42）的读取访问与来自计数器（40）的下部（44）的对应读取访问之间的等待时间期间发生翻转，则从 下部（44）被禁止，并且默认值被置于总线（36）上。
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