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公开(公告)号：US10417004B2
公开(公告)日：2019-09-17
申请号：US15635382
申请日：2017-06-28
Applicant: Altera Corporation
Inventor： Martin Langhammer
Abstract: Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.
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公开(公告)号：US10374636B1
公开(公告)日：2019-08-06
申请号：US15090170
申请日：2016-04-04
Applicant: ALTERA CORPORATION
Inventor： Haiyun Yang , Martin Langhammer , Peng Li , Divya Vijayaraghavan
Abstract: One embodiment relates a method of receiving data from a multi-lane data link. The data is encoded with an FEC code having a block length. The data is FEC encoded at a bus width which is specified within particular constraints. One constraint is that the FEC encoder bus width in bits is an exact multiple of a number of bits per symbol in the data. Another constraint may be that the FEC code block length is an exact multiple of the FEC encoder bus width. Another constraint may be that the FEC encoder bus width is an exact multiple of a number of serial lanes of the multi-lane interface. Other embodiments and features are also disclosed.
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公开(公告)号：US10210919B2
公开(公告)日：2019-02-19
申请号：US14729504
申请日：2015-06-03
Applicant: Altera Corporation
Inventor： Martin Langhammer , Dana How
IPC: G06F1/10 , G11C8/18 , H03K19/177
Abstract: An integrated circuit that includes different types of embedded functional blocks such as programmable logic blocks, memory blocks, and digital signal processing (DSP) blocks is provided. At least a first portion of the functional blocks on the integrated circuit may operate at a normal data rate using a core clock signal while a second portion of the functional blocks on the integrated circuit may operate at a 2× data rate that is double the normal data rate. To support this type of architecture, the integrated circuit may include clock generation circuitry that is capable of providing double pumped clock signals having clock pulses at rising and falling edges of the core clock signal, data concentration circuitry at the input of the 2× functional blocks, and data spreading circuitry at the output of the 2× functional blocks.
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公开(公告)号：US10055195B2
公开(公告)日：2018-08-21
申请号：US15270495
申请日：2016-09-20
Applicant: Altera Corporation
Inventor： Martin Langhammer
CPC classification number: G06F7/50 , G06F5/012 , G06F7/4912 , G06F2205/00 , G06F2207/3816 , G06F2207/48
Abstract: An integrated circuit may include a floating-point adder that supports variable precisions. The floating-point adder may receive first and second inputs to be added, where the first and second inputs each have a mantissa and an exponent. The mantissa and exponent values may be split into a near path and a far path using a dual path floating-point adder architecture depending on the difference of the exponents and on whether an addition or subtraction is being performed. The mantissa values may be left justified, while the sticky bits are right justified. The hardware for the largest mantissa can be used to support the calculations for the smaller mantissas using no additional arithmetic structures, with only some multiplexing and decoding logic.
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5.发明授权公开(公告)号：US10037192B2
公开(公告)日：2018-07-31
申请号：US14919429
申请日：2015-10-21
Applicant: Altera Corporation
Inventor： Martin Langhammer
CPC classification number: G06F7/523 , G06F7/5443 , G06F7/57
Abstract: A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of scaled product sum operations and the implementation of Horner's rule.
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Patent Agency Ranking
公开(公告)号：US09992053B1
公开(公告)日：2018-06-05
申请号：US15421578
申请日：2017-02-01
Applicant: Altera Corporation
Inventor： Martin Langhammer
CPC classification number: H04L29/0651 , G06F21/72 , G06F21/76 , G09C1/00 , H04L9/0643 , H04L29/06517 , H04L29/08081 , H04L2209/125
Abstract: Encryption/authentication circuitry includes an encryption portion having a first number of encryption lanes, each encryption lane including a plurality of encryption stages, and keyspace circuitry including a plurality of key lanes corresponding to a predetermined maximum number of channels. Each key lane has key storage stages corresponding to the encryption stages, and includes key memories for the predetermined maximum number of channels. Key channel selection circuitry for each stage selects a key from among the key memories at that stage. An authentication portion includes a second number of authentication lanes, hash key storage for the predetermined maximum number of channels, partial hash state storage for the predetermined number of channels, and hash channel selection circuitry. Based on the channel being processed, the hash selection circuitry selects, in each respective lane, respective hash key data from the hash key storage and respective partial hash state data from the partial hash state storage.
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公开(公告)号：US20180088906A1
公开(公告)日：2018-03-29
申请号：US15277955
申请日：2016-09-27
Applicant: Altera Corporation
Inventor： Martin Langhammer
CPC classification number: G06F7/483 , G06F7/4812 , G06F7/5443 , G06F17/142 , G06F2207/4812
Abstract: Integrated circuits with specialized processing blocks are provided. A specialized processing block may include one real addition stage and one real multiplier stage. The multiplier stage may simultaneously feed its output to the addition stage and directly to an adjacent specialized processing block. The addition stage may also produce sum and difference outputs in parallel. A group of four such specialized processing blocks may be connected in a chain to implement a radix-2 fast Fourier transform (FFT) butterfly. Multiple radix-2 butterflies may be stacked to form yet higher order radix butterflies. If desired, the specialized processing block may also be used to implement a complex multiply operation. Three or four specialized processing blocks may be chained together and along with one or more adders outside the specialized processing blocks, real and imaginary portions of a complex product can be generated.
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公开(公告)号：US20170371836A1
公开(公告)日：2017-12-28
申请号：US15190716
申请日：2016-06-23
Applicant: Altera Corporation
Inventor： Martin Langhammer
CPC classification number: H03K19/17704 , G06F15/82 , G06F17/5045 , G06F17/5054 , G06F2217/68
Abstract: A programmable integrated circuit may include soft and hard logic for implementing a reduced instruction set computing (RISC) processor. Processor generator tools implemented on specialized computing equipment may be used to specify desired parameters for the processor architecture, including the data word size of one or more data paths, the instruction word size, and a set of instruction formats. The processor generator tools may also be used to determine the appropriate amount of pipelining that is required for each data path to satisfy performance criteria. The processor generator tools can also be used to analyze the processor architecture and to provide options for mitigating potential structural and data hazards.
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公开(公告)号：US20170300337A1
公开(公告)日：2017-10-19
申请号：US15635382
申请日：2017-06-28
Applicant: Altera Corporation
Inventor： Martin Langhammer
Abstract: Circuitry operating under a floating-point mode or a fixed-point mode includes a first circuit accepting a first data input and generating a first data output. The first circuit includes a first arithmetic element accepting the first data input, a plurality of pipeline registers disposed in connection with the first arithmetic element, and a cascade register that outputs the first data output. The circuitry further includes a second circuit accepting a second data input and generating a second data output. The second circuit is cascaded to the first circuit such that the first data output is connected to the second data input via the cascade register. The cascade register is selectively bypassed when the first circuit is operated under the fixed-point mode.
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10.发明授权公开(公告)号：US09787290B2
公开(公告)日：2017-10-10
申请号：US14717449
申请日：2015-05-20
Applicant: Altera Corporation
Inventor： Martin Langhammer , Simon Peter Finn
CPC classification number: H03H17/06 , G06F7/5443 , H03H2220/04 , H03H2220/06
Abstract: Circuitry that accepts a data input and an enable input, and generates an output sum based on the data input includes an input stage circuit that includes an input register. The input register accepts the enable input. The circuitry further includes a systolic register operatively connected to the input stage circuit, and the systolic register is operated without any enable connection. The circuitry further includes a multiplier connected to the systolic register, which is configured to generate a product value. The circuitry further includes an output stage circuit that includes an adder that calculates the output sum based least in part on the product value.
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