公开(公告)号：US20220214982A1

公开(公告)日：2022-07-07

申请号：US17701511

申请日：2022-03-22

申请人： ALTERA CORPORATION

发明人： Arifur Rahman ,  Bernhard Friebe

IPC分类号： G06F13/16 ,  H03K19/003 ,  H03K19/173 ,  G11C7/22 ,  G06F13/40 ,  G06F13/42 ,  G11C8/00 ,  G11C29/12 ,  H01L23/538 ,  H01L25/18 ,  H03K19/1776

摘要： Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.

公开(公告)号：US20220027128A1

公开(公告)日：2022-01-27

申请号：US17493584

申请日：2021-10-04

申请人： Altera Corporation

发明人： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Hyun Yi

IPC分类号： G06F7/485 ,  G06F7/487 ,  G06F7/499 ,  G06F7/483 ,  G06F7/544

摘要： Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.

公开(公告)号：US11157440B2

公开(公告)日：2021-10-26

申请号：US16833068

申请日：2020-03-27

申请人： Altera Corporation

发明人： Chee Hak Teh ,  Arifur Rahman

IPC分类号： G06F13/00 ,  G06F13/40 ,  G06F15/78 ,  G06F13/42 ,  G06F1/06 ,  G06F1/10

摘要： A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US20210216098A1

公开(公告)日：2021-07-15

申请号：US17214594

申请日：2021-03-26

申请人： ALTERA CORPORATION

发明人： Mark Bourgeault

IPC分类号： G06F1/10 ,  G06F1/06 ,  G06F30/331 ,  G06F30/3312 ,  G06F30/392 ,  G06F30/394 ,  H03K19/173 ,  H03L7/07 ,  G06F30/39

摘要： An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.

公开(公告)号：US11016742B2

公开(公告)日：2021-05-25

申请号：US14749379

申请日：2015-06-24

申请人： Altera Corporation

发明人： Alan Baker ,  Andrew Chaang Ling ,  Andrei Mihai Hagiescu Miriste

IPC分类号： G06F8/41 ,  G06F8/40 ,  G06F30/34 ,  G06F30/327 ,  G06F115/08 ,  G06F9/54

摘要： Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.

公开(公告)号：US10970409B1

公开(公告)日：2021-04-06

申请号：US15389886

申请日：2016-12-23

申请人： Altera Corporation

发明人： Martin Langhammer

IPC分类号： G06F12/14 ,  G06F21/62 ,  H04L9/32 ,  H04L9/06 ,  H04L29/06

摘要： Circuits, methods, and apparatus for storing application data, keys, authorization codes, or other information in a volatile memory on an FPGA. A field programmable gate array (FPGA) can include multiple memory blocks and partition those blocks among multiple independent reconfigurable regions. Access to the memory blocks can then be restricted so that only authorized regions have access to particular memory partitions. In addition, each partition can store multiple message authentication codes (MACs) for further controlling access to data in each partition.

公开(公告)号：US10969820B2

公开(公告)日：2021-04-06

申请号：US16415619

申请日：2019-05-17

申请人： ALTERA CORPORATION

发明人： Mark Bourgeault

IPC分类号： G06F1/10 ,  H03K19/173 ,  G06F30/39 ,  G06F30/331 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3312 ,  G06F1/06 ,  H03L7/07 ,  H03K3/037

摘要： An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.

公开(公告)号：US10958411B2

公开(公告)日：2021-03-23

申请号：US16841622

申请日：2020-04-06

申请人： Altera Corporation

发明人： Boon Hong Oh ,  Chee Seng Tan ,  Chau Perng Chin

IPC分类号： H03L7/00 ,  H04L7/00 ,  H04L7/033

摘要： Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.

公开(公告)号：US10936531B2

公开(公告)日：2021-03-02

申请号：US16792507

申请日：2020-02-17

申请人： Altera Corporation

发明人： Gary Brian Wallichs ,  Keith Duwel ,  Cora Lynn Mau

IPC分类号： G06F13/42 ,  H04L29/06 ,  G06F5/06 ,  H04L12/947

摘要： Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

公开(公告)号：US20210021268A1

公开(公告)日：2021-01-21

申请号：US17062421

申请日：2020-10-02

申请人： Altera Corporation

发明人： Tony K. Ngai

IPC分类号： H03K19/0175 ,  H01L25/065 ,  H03K19/17736

摘要： A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.