公开(公告)号：US20240235902A1

公开(公告)日：2024-07-11

申请号：US18617467

申请日：2024-03-26

申请人： Altera Corporation

发明人： Mitchell Cooke

IPC分类号： H04L25/03

CPC分类号： H04L25/03057 ,  H04L25/03267

摘要： A device of the present disclosure may include interface circuitry and a decision feedback equalization (DFE) tuner. The interface circuitry may be coupled to DFE circuitry by data interconnect. The DFE tuner may control adaptation of the DFE circuitry to a channel associated with the data interconnect using an oscillating reference voltage provided to the DFE circuitry. The interface circuitry may be coupled between the DFE tuner and the DFE circuitry.

公开(公告)号：US20240213985A1

公开(公告)日：2024-06-27

申请号：US18601665

申请日：2024-03-11

申请人： Altera Corporation

发明人： Arch Zaliznyak ,  Archanna Srinivasan ,  Gregory Steinke

IPC分类号： H03K19/173 ,  H01L23/00 ,  H01L23/538 ,  H01L25/10

CPC分类号： H03K19/173 ,  H01L23/5386 ,  H01L25/105 ,  H01L24/16 ,  H01L2224/16225

摘要： A circuit system includes an interposer comprising conductors and switch circuits coupled to the conductors, a first integrated circuit die coupled to the interposer, and a second integrated circuit die coupled to the interposer. The first integrated circuit die comprises a primary controller circuit for configuring the switch circuits. The second integrated circuit die comprises a secondary controller circuit. The primary controller circuit configures configurable logic circuits in the second integrated circuit die by providing configuration bits to the secondary controller circuit through the interposer.

公开(公告)号：US20240104136A1

公开(公告)日：2024-03-28

申请号：US18520358

申请日：2023-11-27

申请人： Altera Corporation

发明人： Johan KARLSSON RÖNNBERG ,  Mikael SUNDSTRÖM

IPC分类号： G06F16/901 ,  G06F16/22 ,  G06F16/2453 ,  G06F16/2455

CPC分类号： G06F16/9024 ,  G06F16/2246 ,  G06F16/24542 ,  G06F16/24554

摘要： Methods, apparatus, and systems for efficient partitioning and construction of graphs for scalable high-performance search applications. A method for partitioning a set of ternary keys having one or more wildcards includes analyzing patterns of the set of ternary keys and storing ternary keys with the same pattern in the same subset. The patterns may include uncompressed patterns and compressed patterns. When there are more patterns than a target number of subgraphs, patterns are repeatedly merged until the number of merged patterns matches the target number of subgraphs. Table entries having ternary keys corresponding to the ternary keys in a final set of merged patterns of ternary keys are generated and partitioned into sub-tables, with each sub-table associated with a respective sub-graph. Tables with hundreds of thousands or millions of entries are supported.

公开(公告)号：US11741042B2

公开(公告)日：2023-08-29

申请号：US17561917

申请日：2021-12-24

申请人： Altera Corporation

发明人： Chee Hak Teh ,  Arifur Rahman

IPC分类号： G06F15/78 ,  G06F13/42 ,  G06F13/40 ,  G06F1/06 ,  G06F1/10

CPC分类号： G06F15/7803 ,  G06F1/06 ,  G06F1/10 ,  G06F13/4022 ,  G06F13/4234 ,  G06F13/4291 ,  G06F15/7864 ,  Y02D10/00

摘要： A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US11675613B2

公开(公告)日：2023-06-13

申请号：US17024619

申请日：2020-09-17

申请人： ALTERA CORPORATION

发明人： Jiefan Zhang ,  Abdel Hafiz Rabi ,  Allen Chen ,  Mark Jonathan Lewis

IPC分类号： G06F9/455 ,  G06F9/54 ,  G06F15/78

CPC分类号： G06F9/45558 ,  G06F9/45533 ,  G06F9/54 ,  G06F15/7867 ,  G06F15/7889 ,  G06F2009/4557

摘要： Techniques and mechanisms provide a flexible mapping for physical functions and virtual functions in an environment including virtual machines.

公开(公告)号：US20220214982A1

公开(公告)日：2022-07-07

申请号：US17701511

申请日：2022-03-22

申请人： ALTERA CORPORATION

发明人： Arifur Rahman ,  Bernhard Friebe

IPC分类号： G06F13/16 ,  H03K19/003 ,  H03K19/173 ,  G11C7/22 ,  G06F13/40 ,  G06F13/42 ,  G11C8/00 ,  G11C29/12 ,  H01L23/538 ,  H01L25/18 ,  H03K19/1776

摘要： Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.

公开(公告)号：US20220027128A1

公开(公告)日：2022-01-27

申请号：US17493584

申请日：2021-10-04

申请人： Altera Corporation

发明人： Keone Streicher ,  Martin Langhammer ,  Yi-Wen Lin ,  Hyun Yi

IPC分类号： G06F7/485 ,  G06F7/487 ,  G06F7/499 ,  G06F7/483 ,  G06F7/544

摘要： Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.

公开(公告)号：US11157440B2

公开(公告)日：2021-10-26

申请号：US16833068

申请日：2020-03-27

申请人： Altera Corporation

发明人： Chee Hak Teh ,  Arifur Rahman

IPC分类号： G06F13/00 ,  G06F13/40 ,  G06F15/78 ,  G06F13/42 ,  G06F1/06 ,  G06F1/10

摘要： A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US20210216098A1

公开(公告)日：2021-07-15

申请号：US17214594

申请日：2021-03-26

申请人： ALTERA CORPORATION

发明人： Mark Bourgeault

IPC分类号： G06F1/10 ,  G06F1/06 ,  G06F30/331 ,  G06F30/3312 ,  G06F30/392 ,  G06F30/394 ,  H03K19/173 ,  H03L7/07 ,  G06F30/39

摘要： An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.

公开(公告)号：US11016742B2

公开(公告)日：2021-05-25

申请号：US14749379

申请日：2015-06-24

申请人： Altera Corporation

发明人： Alan Baker ,  Andrew Chaang Ling ,  Andrei Mihai Hagiescu Miriste

IPC分类号： G06F8/41 ,  G06F8/40 ,  G06F30/34 ,  G06F30/327 ,  G06F115/08 ,  G06F9/54

摘要： Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.