公开(公告)号：US09419076B1

公开(公告)日：2016-08-16

申请号：US14563363

申请日：2014-12-08

申请人： Altera Corporation

发明人： Weimin Zhang ,  Yanzhong Xu

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/737 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/16 ,  H01L21/308 ,  H01L29/739 ,  H01L29/73

CPC分类号： H01L29/66795 ,  H01L21/3086 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/41708 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732 ,  H01L29/739 ,  H01L29/785

摘要： A bipolar junction transistor (BJT) is formed in a thin (less than about 20 nanometers) segment of a semiconductive material such as silicon where a lower portion of the semiconductive material has doping of a first conductivity type and forms a collector and an upper portion of the semiconductive material has doping of a second conductivity type and forms a base. Either a metal or a polysilicon emitter is formed on the base. An illustrative method for forming the BJT comprises forming first and second layers of a semiconductive material having first and second conductivity types, respectively; forming a hard mask on an upper surface of the second layer; using the hard mask to etch first and second channels in the semiconductive material on first and second opposing sides of the hard mask; removing the hard mask; and forming an emitter on the upper surface of the second layer.

摘要翻译： 双极结型晶体管（BJT）形成在诸如硅的半导体材料的薄（小于约20纳米）的段中，其中半导体材料的下部具有掺杂第一导电类型并形成集电极和上部 的半导体材料具有第二导电类型的掺杂并形成基底。 在基底上形成金属或多晶硅发射体。 用于形成BJT的说明性方法包括分别形成具有第一和第二导电类型的半导体材料的第一和第二层; 在第二层的上表面上形成硬掩模; 使用硬掩模来蚀刻硬掩模的第一和第二相对侧上的半导体材料中的第一和第二通道; 去除硬面膜; 以及在所述第二层的上表面上形成发射体。

公开(公告)号：US09559699B1

公开(公告)日：2017-01-31

申请号：US15004683

申请日：2016-01-22

申请人： ALTERA CORPORATION

发明人： Weimin Zhang ,  Yanzhong Xu

IPC分类号： H03K19/177 ,  H03K17/687 ,  H03M1/66 ,  H03K5/159

CPC分类号： H03K19/1774 ,  H03K5/159 ,  H03M1/661

摘要： A method and apparatus for reducing global interconnect delay on a field programmable gate array (FPGA) on an integrated circuit die comprising coding with a digital to analog coder on the integrated circuit die successive groups of n digital bits into an 2n level voltage or current signal where n is an integer greater than or equal to 2; transmitting the voltage or current signal on a global interconnect on the integrated circuit die; receiving on the integrated circuit die the signal transmitted on the global interconnect; and decoding the received signal on the integrated circuit die to reconstitute the successive groups of digital bits.

摘要翻译： 一种用于减少集成电路管芯上的现场可编程门阵列（FPGA）上的全局互连延迟的方法和装置，其包括利用集成电路上的数模转换器对连续的n个数字位组进行编码为2n电平电压或电流信号 其中n是大于或等于2的整数; 在集成电路管芯上的全局互连上传输电压或电流信号; 在集成电路上接收在全局互连上传输的信号; 以及对集成电路管芯上的接收信号进行解码以重构连续的数字位组。

公开(公告)号：US09508720B1

公开(公告)日：2016-11-29

申请号：US14677448

申请日：2015-04-02

申请人： Altera Corporation

发明人： Weimin Zhang ,  Yanzhong Xu

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/16

CPC分类号： H01L27/0924 ,  H01L21/823814 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/785

摘要： An illustrative finFET comprises first, second, and third pluralities of fins having gate structures and source and drain regions formed on the fins so that first PMOS transistors are formed in first epitaxial regions on the first plurality of fins, NMOS transistors are formed in second epitaxial regions on the second plurality of fins and second PMOS transistors are formed in third epitaxial regions on the third plurality of fins. In three embodiments, the fins are formed in silicon; the first epitaxial region is silicon germanium; the second region is silicon; and the third region is 1) silicon, 2) silicon carbide, or 3) silicon or silicon carbide on a silicon carbide cladding. In another embodiment, the third epitaxial regions are wide band gap semiconductors formed on wide band gap semiconductor fins. In another embodiment, all the fins and epitaxial regions are wide band gap semiconductors.

摘要翻译： 一个说明性的finFET包括第一，第二和第三个鳍片，其具有形成在鳍片上的栅极结构和源极和漏极区域，使得第一PMOS晶体管形成在第一多个鳍片上的第一外延区域中，NMOS晶体管形成在第二外延 第二多个翅片上的区域和第二PMOS晶体管形成在第三多个鳍片上的第三外延区域中。 在三个实施例中，翅片形成在硅中; 第一外延区是硅锗; 第二区是硅; 并且第三区域是1）硅，2）碳化硅，或3）在碳化硅包层上的硅或碳化硅。 在另一个实施例中，第三外延区域是形成在宽带隙半导体鳍片上的宽带隙半导体。 在另一个实施例中，所有鳍片和外延区域都是宽带隙半导体。