SILICON-CONTROLLED RECTIFICATION DEVICE WITH HIGH EFFICIENCY
    1.
    发明申请
    SILICON-CONTROLLED RECTIFICATION DEVICE WITH HIGH EFFICIENCY 有权
    具有高效率的硅控制整流装置

    公开(公告)号:US20150194511A1

    公开(公告)日:2015-07-09

    申请号:US14662417

    申请日:2015-03-19

    IPC分类号: H01L29/747

    摘要: A silicon-controlled rectification device with high efficiency is disclosed, which comprises a P-type region surrounding an N-type region. A first P-type heavily doped area is arranged in the N-type region and connected with a high-voltage terminal. A plurality of second N-type heavily doped areas is arranged in the N-type region. A plurality of second P-type heavily doped areas is closer to the second N-type heavily doped areas than the first N-type heavily doped area and arranged in the P-type region. At least one third N-type heavily doped area is arranged in the P-type region and connected with a low-voltage terminal.Alternatively or in combination, the second N-type heavily doped areas and the second P-type heavily doped areas are respectively arranged in the P-type region and the N-type region.

    摘要翻译: 公开了一种高效率的硅控整流装置,其包括围绕N型区域的P型区域。 第一P型重掺杂区域布置在N型区域中并与高压端子连接。 在N型区域中布置有多个第二N型重掺杂区域。 多个第二P型重掺杂区域比第一N型重掺杂区域更靠近第二N型重掺杂区域并且布置在P型区域中。 在P型区域中设置至少一个第三N型重掺杂区域,并与低电压端子连接。 或者或组合地,第二N型重掺杂区域和第二P型重掺杂区域分别布置在P型区域和N型区域中。

    METHOD FOR FABRICATING A PLANAR MICRO-TUBE DISCHARGER STRUCTURE
    2.
    发明申请
    METHOD FOR FABRICATING A PLANAR MICRO-TUBE DISCHARGER STRUCTURE 审中-公开
    制造平面微管排放结构的方法

    公开(公告)号:US20140106064A1

    公开(公告)日:2014-04-17

    申请号:US14109297

    申请日:2013-12-17

    IPC分类号: H01J9/02

    CPC分类号: H01J9/02 H01J17/066

    摘要: A method for fabricating a semiconductor-based planar micro-tube discharger structure is provided, including the steps of forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap, forming an insulating layer over the patterned electrodes and the separating block., and filling the insulating layer into the gap. At least two discharge paths are formed. The method can fabricate a plurality of discharge paths in a semiconductor structure, the structure having very high reliability and reusability.

    摘要翻译: 提供一种制造基于半导体的平面微管放电器结构的方法,包括以下步骤:在衬底上形成由间隙分开的两个图案化电极和布置在间隙中的至少一个分隔块,在图案上形成绝缘层 电极和分离块,并将绝缘层填充到间隙中。 形成至少两个排出路径。 该方法可以在半导体结构中制造多个放电路径,该结构具有非常高的可靠性和可再利用性。

    SERIAL TRANSMISSION DRIVING METHOD
    3.
    发明申请
    SERIAL TRANSMISSION DRIVING METHOD 有权
    串行传输驱动方法

    公开(公告)号:US20150145557A1

    公开(公告)日:2015-05-28

    申请号:US14199448

    申请日:2014-03-06

    摘要: The present invention discloses a serial transmission driving method, wherein a serial transmission driving device (STD) is connected with a first terminal (FT) and a second terminal (ST) of an equivalent load capacitor through a first differential bus (FDB) and a second differential bus (SDB). FDB and SDB are respectively connected with a high-potential terminal (HPT) and a low-potential terminal (LPT) through a first equivalent resistor and a second equivalent resistor. STD receives a trigger signal (TS) appearing during the transition between a turn-on signal (Ton) and a turn-off signal (Toff), generates a first potential (FP) and a second potential (SP) greater than FP according to TS, and respectively applies FP and SP to SDB and FDB. FP and SP fast change the potential of FT to be greater than that of ST. HPT and LPT maintain potentials of FDB and SDB until Toff ends.

    摘要翻译: 本发明公开了一种串行传输驱动方法,其中串行传输驱动装置(STD)通过第一差分总线(FDB)与等效负载电容器的第一端子(FT)和第二端子(ST)连接, 第二差分总线(SDB)。 FDB和SDB分别通过第一等效电阻器和第二等效电阻器与高电位端子(HPT)和低电位端子(LPT)连接。 STD接收在导通信号(Ton)和关断信号(Toff)之间的转换期间出现的触发信号(TS),根据下列情况产生大于FP的第一电位(FP)和第二电位(SP) TS,并分别将FP和SP应用于SDB和FDB。 FP和SP快速将FT的潜力更大于ST的潜力。 HPT和LPT保持FDB和SDB的潜力,直到Toff结束。

    SILICON-CONTROLLED-RECTIFIER WITH ADJUSTABLE HOLDING VOLTAGE
    4.
    发明申请
    SILICON-CONTROLLED-RECTIFIER WITH ADJUSTABLE HOLDING VOLTAGE 审中-公开
    具有可调节保持电压的硅控制整流器

    公开(公告)号:US20140299912A1

    公开(公告)日:2014-10-09

    申请号:US14309660

    申请日:2014-06-19

    IPC分类号: H01L29/74

    摘要: In a silicon-controlled-rectifier (SCR) with adjustable holding voltage, an epitaxial layer is formed on a heavily doped semiconductor layer. A first N-well having a first P-heavily doped area is formed in the epitaxial layer. A first P-well is formed in the epitaxial layer. Besides, a first N-heavily doped area is formed in the first P-well. At least one deep isolation trench is formed in the epitaxial layer, having a depth greater than the depth of the first N-type well and located between the first P-heavily doped area and the first N-heavily doped area. A distance between the deep isolation trench and the heavily doped semiconductor layer is larger than zero.

    摘要翻译: 在具有可调保持电压的硅控整流器(SCR)中,在重掺杂半导体层上形成外延层。 在外延层中形成具有第一P重掺杂区的第一N阱。 在外延层中形成第一P阱。 此外,在第一P阱中形成第一N重掺杂区域。 在外延层中形成至少一个深的隔离沟槽,其深度大于第一N型阱的深度并且位于第一P重掺杂区域和第一N重掺杂区域之间。 深隔离沟槽和重掺杂半导体层之间的距离大于零。