公开(公告)号：US12271669B1

公开(公告)日：2025-04-08

申请号：US17709192

申请日：2022-03-30

Applicant: Amazon Technologies, Inc.

Inventor： Uri Leder ,  Ori Ariel ,  Assaf Fainer ,  Simaan Bahouth ,  Max Chvalevsky ,  Itai Kahana

IPC: G06F30/30 ,  G06F30/3323 ,  G06F30/367

Abstract: Generated instruction sequences captured from software interactions may be executed as part of formal verification of a design under test. Software-instructed commands to be performed to configure a design under test formatted according to an interface implemented by the design under test can be obtained. A sequence to perform the software-instructed commands may be generated to configure the design under test in a hardware design and verification language. The sequence may then be executed to perform the software-instructed commands to configure the design under test and then perform formal verification on the configured design under test.

公开(公告)号：US11954495B1

公开(公告)日：2024-04-09

申请号：US17643777

申请日：2021-12-10

Applicant: Amazon Technologies, Inc.

Inventor： Michael Shteinbok ,  Yaniv Halmut ,  Jonathan Cohen ,  Nofar Mann ,  Tamir Malka ,  Amit Abecasis ,  Assaf Fainer

IPC: G06F9/38 ,  G06F16/245 ,  G06F16/2455

CPC classification number: G06F9/3877 ,  G06F16/245 ,  G06F16/2455 ,  G06F16/24569

Abstract: To accelerate the data processing of a processor, a coprocessor subsystem can be used to offload data processing operations from the processor. The coprocessor subsystem can include a coprocessor and an accelerator. The accelerator can offload operations such as data formatting operations from the coprocessor to improve the performance of the coprocessor. The coprocessor subsystem can be used to accelerate database operations.