公开(公告)号：US11544436B1

公开(公告)日：2023-01-03

申请号：US17353715

申请日：2021-06-21

Applicant: Amazon Technologies, Inc.

Inventor： Uri Leder ,  Ori Cohen ,  Benzi Denkberg ,  Max Chvalevsky

IPC: G06F30/3323 ,  G01R31/317 ,  G06F30/31 ,  G06F117/08

Abstract: Hardware-software interaction testing is performed using formal verification for language-specified hardware designs. A description of valid access using an interface for a configuration space of a language specified hardware design and a description of a valid output of the language-specified hardware design is received. Formal verification is performed on the language-specified hardware design using the interface for the configuration space according to the description of valid access using the interface. A sequence of access to the configuration space using the interface that causes a failure to produce the valid output of the language-specified hardware design according to the description of valid output to identify as an error for the language-specified hardware design.

公开(公告)号：US12175178B1

公开(公告)日：2024-12-24

申请号：US17457807

申请日：2021-12-06

Applicant: Amazon Technologies, Inc.

Inventor： Max Chvalevsky ,  Uri Leder

IPC: G06F30/3323

Abstract: A fuzzy scoreboard can compute, using a signature function, a first signature of an expected data stream associated with an input data stream that is being inputted to a design-under-test (DUT) for a datapath test. The first signature of the expected data stream can be stored without storing the expected data stream. The fuzzy scoreboard can also compute, using the same signature function, a second signature of an output data stream that is outputted from the DUT during the datapath test. The first signature can be compared with the second signature to determine whether there is a match. Storing the first signature of the expected data stream without storing the expected data stream can reduce the memory space consumed by the fuzzy scoreboard.

公开(公告)号：US11768990B1

公开(公告)日：2023-09-26

申请号：US17305043

申请日：2021-06-29

Applicant: Amazon Technologies, Inc.

Inventor： Uri Leder ,  Ori Ariel ,  Max Chvalevsky ,  Benzi Denkberg ,  Guy Nakibly

IPC: G06F30/398 ,  G06F30/394 ,  G06F30/331 ,  G06F30/392

CPC classification number: G06F30/394 ,  G06F30/331 ,  G06F30/392 ,  G06F30/398

Abstract: An integrated circuit design technique utilizes a data structure describing the connections, interconnect routing information of the connections, and bandwidth requirements of the connections in an integrated circuit device to generate an interconnect flow graph having nodes, and edges connecting the nodes. The edges connecting the nodes can reflect the bandwidth requirements of the connections. The interconnect flow graph can be used to optimize and verify the integrated circuit design.

公开(公告)号：US11062077B1

公开(公告)日：2021-07-13

申请号：US16450326

申请日：2019-06-24

Applicant: Amazon Technologies, Inc.

Inventor： Max Chvalevsky

IPC: G06F9/455 ,  G06F30/398 ,  G06F30/3323

Abstract: Bit-reduction in a verification processes for memory arrays is disclosed. Properties are determined for verification of a circuit that includes a memory array. Circuit data for the circuit is received in a verification environment. When it is determined that the circuit includes a memory array, an address for the memory array is sampled as part of a read operation during verification for the circuit. A determination may be made that the circuit is in compliance with a property of the properties based at least in part on compliance of the read operation with a predetermined model. The sampling of the address replicates a delay expected in physical read operation of the memory array, but with reduced bits communicated or generated per cycle in the verification process because output data is not sampled contrasting the physical read operation.