公开(公告)号：US10298496B1

公开(公告)日：2019-05-21

申请号：US15716036

申请日：2017-09-26

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Benzi Denkberg ,  Erez Izenberg ,  Nafea Bshara ,  Uri Leder ,  Ofer Frishman

IPC: H04L12/747 ,  H04L12/861 ,  G06F12/0802 ,  H04L29/06 ,  H04L12/931

Abstract: A data or packet processing device such as a network interface controller may include cache control logic that is configured to receive a first request for processing a first data packet associated with the queue identifier, and obtain a set of memory descriptors associated with the queue identifier from the memory. The set of descriptors can be stored in the cache. When a second request for processing a second data packet associated with the queue identifier is received, the cache control logic can determine that the cache is storing memory descriptors for processing the second data packet, and provide the memory descriptors used for processing the second packet.

公开(公告)号：US11768990B1

公开(公告)日：2023-09-26

申请号：US17305043

申请日：2021-06-29

Applicant: Amazon Technologies, Inc.

Inventor： Uri Leder ,  Ori Ariel ,  Max Chvalevsky ,  Benzi Denkberg ,  Guy Nakibly

IPC: G06F30/398 ,  G06F30/394 ,  G06F30/331 ,  G06F30/392

CPC classification number: G06F30/394 ,  G06F30/331 ,  G06F30/392 ,  G06F30/398

Abstract: An integrated circuit design technique utilizes a data structure describing the connections, interconnect routing information of the connections, and bandwidth requirements of the connections in an integrated circuit device to generate an interconnect flow graph having nodes, and edges connecting the nodes. The edges connecting the nodes can reflect the bandwidth requirements of the connections. The interconnect flow graph can be used to optimize and verify the integrated circuit design.

公开(公告)号：US12271669B1

公开(公告)日：2025-04-08

申请号：US17709192

申请日：2022-03-30

Applicant: Amazon Technologies, Inc.

Inventor： Uri Leder ,  Ori Ariel ,  Assaf Fainer ,  Simaan Bahouth ,  Max Chvalevsky ,  Itai Kahana

IPC: G06F30/30 ,  G06F30/3323 ,  G06F30/367

Abstract: Generated instruction sequences captured from software interactions may be executed as part of formal verification of a design under test. Software-instructed commands to be performed to configure a design under test formatted according to an interface implemented by the design under test can be obtained. A sequence to perform the software-instructed commands may be generated to configure the design under test in a hardware design and verification language. The sequence may then be executed to perform the software-instructed commands to configure the design under test and then perform formal verification on the configured design under test.

公开(公告)号：US11544436B1

公开(公告)日：2023-01-03

申请号：US17353715

申请日：2021-06-21

Applicant: Amazon Technologies, Inc.

Inventor： Uri Leder ,  Ori Cohen ,  Benzi Denkberg ,  Max Chvalevsky

IPC: G06F30/3323 ,  G01R31/317 ,  G06F30/31 ,  G06F117/08

Abstract: Hardware-software interaction testing is performed using formal verification for language-specified hardware designs. A description of valid access using an interface for a configuration space of a language specified hardware design and a description of a valid output of the language-specified hardware design is received. Formal verification is performed on the language-specified hardware design using the interface for the configuration space according to the description of valid access using the interface. A sequence of access to the configuration space using the interface that causes a failure to produce the valid output of the language-specified hardware design according to the description of valid output to identify as an error for the language-specified hardware design.

公开(公告)号：US10911358B1

公开(公告)日：2021-02-02

申请号：US16384745

申请日：2019-04-15

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Benzi Denkberg ,  Erez Izenberg ,  Nafea Bshara ,  Uri Leder ,  Ofer Frishman

IPC: H04L12/747 ,  G06F12/0802 ,  H04L12/861 ,  H04L12/931 ,  H04L29/06

Abstract: A data or packet processing device such as a network interface controller may include cache control logic that is configured to obtain a set of memory descriptors associated with a queue from the memory. The set of descriptors can be stored in the cache. When a request for processing a data packet associated with the queue is received, the cache control logic can determine that the cache is storing memory descriptors for processing the data packet, and provide the memory descriptors used for processing the packet.

公开(公告)号：US12175178B1

公开(公告)日：2024-12-24

申请号：US17457807

申请日：2021-12-06

Applicant: Amazon Technologies, Inc.

Inventor： Max Chvalevsky ,  Uri Leder

IPC: G06F30/3323

Abstract: A fuzzy scoreboard can compute, using a signature function, a first signature of an expected data stream associated with an input data stream that is being inputted to a design-under-test (DUT) for a datapath test. The first signature of the expected data stream can be stored without storing the expected data stream. The fuzzy scoreboard can also compute, using the same signature function, a second signature of an output data stream that is outputted from the DUT during the datapath test. The first signature can be compared with the second signature to determine whether there is a match. Storing the first signature of the expected data stream without storing the expected data stream can reduce the memory space consumed by the fuzzy scoreboard.

公开(公告)号：US11182103B1

公开(公告)日：2021-11-23

申请号：US16261198

申请日：2019-01-29

Applicant: Amazon Technologies, Inc.

Inventor： Itai Avron ,  Adi Habusha ,  Uri Leder ,  Svetlana Kantorovych

IPC: G06F3/06 ,  G06F12/0806 ,  G06F12/0875 ,  G06F12/0873

Abstract: A dedicated input/output (I/O) cache can be used for I/O-to-processor communications. Data received from an I/O device can be written to the I/O cache and also written to a device memory that is accessible to the processor. The processor can then access the data in the fast, dedicated I/O cache if available. Otherwise, the processor can read the data from the memory into a conventional processor cache for processing. Writes to the cache can be full or partial, with partial writes utilizing padding in some embodiments. The data can be written sequentially in a circular manner. Data processed by the processor can be invalidated, and invalidated data can be overwritten on a subsequent write. Phase bits can also be used to indicate the pass during which various writes were performed.

公开(公告)号：US10929584B1

公开(公告)日：2021-02-23

申请号：US16712933

申请日：2019-12-12

Applicant: Amazon Technologies, Inc.

Inventor： Benzi Denkberg ,  Uri Leder ,  Ori Weber

IPC: G06F30/33 ,  G06F5/06 ,  G06F30/3323

Abstract: Environmental modification testing with a formal verification is implemented for language-specified hardware designs. A language-specified hardware design may be received. A reference copy of the language-specified hardware design may be created. A formal verification may be performed on both the language-specified hardware design and the reference copy with a same input data. Different environmental assumptions for processing the same input data through the reference copy and the language-specified hardware design may be applied. An output value of the language-specified hardware design may be compared with an output value of the reference copy to determine whether those output values match. Error indications may be provided based on a result of the comparison.

公开(公告)号：US10228869B1

公开(公告)日：2019-03-12

申请号：US15716010

申请日：2017-09-26

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Benzi Denkberg ,  Ofer Frishman ,  Erez Izenberg ,  Uri Leder ,  Nafea Bshara

IPC: G06F9/48 ,  G06F3/06 ,  H04L12/911 ,  G06F9/50 ,  H04L29/08

Abstract: Techniques for controlling access to shared resources may include receiving multiple requests to access shared information associated with an identifier. For each of the requests, an entry in a linked list can be allocated to the request, and each entry can be associated with the identifier. The shared information associated with the identifier can be retrieved, and stored in each entry associated with the identifier. A conflict indicator is set in each entry to indicate whether the shared information is available for the request corresponding to the entry. The shared information stored in each entry is provided for each request after the conflict indicator in the corresponding entry indicates the shared information is available for the request.