公开(公告)号：US11909850B1

公开(公告)日：2024-02-20

申请号：US17304593

申请日：2021-06-23

Applicant: Amazon Technologies, Inc.

Inventor： Gal Kochavi ,  Itai Avron ,  Benny Pollak

IPC: H04L69/18 ,  H04L1/00 ,  H04L43/18

CPC classification number: H04L69/18 ,  H04L1/001 ,  H04L1/0018 ,  H04L43/18 ,  H04L2212/00

Abstract: Systems and methods are provided to improve a communication channel dynamically and autonomously based on the status of the communication traffic on the communication channel between a first integrated circuit (IC) and a second IC. The communication traffic on the communication channel can be monitored, and latency, bandwidth, link quality, or power consumption associated with the communication channel for the monitored communication traffic can be determined dynamically. A modified protocol for the communication channel that can improve the communication channel as compared to an existing protocol can be determined based on the information related to the latency, bandwidth, link quality, or the power consumption. The existing protocol can be changed autonomously to the modified protocol as the communication traffic varies.

公开(公告)号：US10705985B1

公开(公告)日：2020-07-07

申请号：US15918930

申请日：2018-03-12

Applicant: Amazon Technologies, Inc.

Inventor： Benny Pollak ,  Dana Michelle Vantrease ,  Adi Habusha

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/16

Abstract: In various implementations, provided are systems and methods for an integrated circuit implementing a processor that can include a rate limiting circuit that attempts to fairly distribute processor memory bandwidth between transaction generators in the processor. The rate limiting circuit can maintain a count of tokens for each transaction generator, where a transaction generator can only transmit a transaction when the transaction generator has enough tokens to do so. Each transaction generator can send a request to the rate limiting circuit when the transaction generator wants to transmit a transaction. The rate limiting circuit can then check whether the transaction generator has sufficient tokens to transmit the transaction. When the transaction generator has enough tokens, the rate limiting circuit will allow the transaction to enter the interconnect. When the transaction generator does not have enough tokens, the rate limiting circuit will not allow the transaction to enter the interconnect.

公开(公告)号：US11789807B1

公开(公告)日：2023-10-17

申请号：US17301254

申请日：2021-03-30

Applicant: Amazon Technologies, Inc.

Inventor： Gal Kochavi ,  Benny Pollak ,  Sergey Kleyman ,  Itai Avron

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/079 ,  G06F11/0751

Abstract: Systems and methods are disclosed to provide an autonomous management of communication links between dice on a multi-die assembly. Each die can include a detection unit and a controller to detect a failing communication link and perform link maintenance by directing the communication traffic on the failing link to an operational link before the link fails. Once the failing link has been repaired, the controller can re-direct the traffic back to the repaired link. The controllers on each die can negotiate through a handshake process to provide the continuous operation by switching the communication traffic from the failing link to the operational link, and then from the operational link to the repaired link.

公开(公告)号：US11782865B1

公开(公告)日：2023-10-10

申请号：US17303561

申请日：2021-06-02

Applicant: Amazon Technologies, Inc.

Inventor： Gal Kochavi ,  Benny Pollak

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/16 ,  G06F13/20

CPC classification number: G06F13/4221 ,  G06F13/1673 ,  G06F13/1678 ,  G06F13/20 ,  G06F13/161

Abstract: An integrated circuit can be used to regulate data flow in a computing system. The integrated circuit can receive input data via a first interface associated with a first type of bus protocol and provide output data via a second interface associated with a second type of bus protocol. Size of the input data and the output data may vary based on the corresponding protocols. The integrated circuit can receive, via the first interface, an input data size for a write transaction to store the input data in a data storage unit. The integrated circuit can also receive a requested data size, via the second interface, to provide the output data for a read transaction. The integrated circuit can also generate an actual size of the output data based on the requested data size, the input data size, and size of the stored input data.