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公开(公告)号:US10911358B1
公开(公告)日:2021-02-02
申请号:US16384745
申请日:2019-04-15
Applicant: Amazon Technologies, Inc.
Inventor: Guy Nakibly , Benzi Denkberg , Erez Izenberg , Nafea Bshara , Uri Leder , Ofer Frishman
IPC: H04L12/747 , G06F12/0802 , H04L12/861 , H04L12/931 , H04L29/06
Abstract: A data or packet processing device such as a network interface controller may include cache control logic that is configured to obtain a set of memory descriptors associated with a queue from the memory. The set of descriptors can be stored in the cache. When a request for processing a data packet associated with the queue is received, the cache control logic can determine that the cache is storing memory descriptors for processing the data packet, and provide the memory descriptors used for processing the packet.
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公开(公告)号:US20190215021A1
公开(公告)日:2019-07-11
申请号:US16241275
申请日:2019-01-07
Applicant: Amazon Technologies, Inc.
Inventor: Ofer Frishman , Erez Izenberg , Guy Nakibly
Abstract: Systems and methods in accordance with various embodiments of the present disclosure provide approaches for mapping entries to a cache using a function, such as cyclic redundancy check (CRC). The function can calculate a colored cache index based on a main memory address. The function may cause consecutive address cache indexes to be spread throughout the cache according to the indexes calculated by the function. In some embodiments, each data context may be associated with a different function, enabling different types of packets to be processed while sharing the same cache, reducing evictions of other data contexts and improving performance. Various embodiments can identify a type of packet as the packet is received, and lookup a mapping function based on the type of packet. The function can then be used to lookup the corresponding data context for the packet from the cache, for processing the packet.
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公开(公告)号:US10790862B2
公开(公告)日:2020-09-29
申请号:US16241275
申请日:2019-01-07
Applicant: Amazon Technologies, Inc.
Inventor: Ofer Frishman , Erez Izenberg , Guy Nakibly
IPC: H03M13/00 , H04L29/06 , G06F12/12 , G06F12/0813 , G06F11/10 , H03M13/09 , G06F12/0864 , G06F12/084 , G06F12/0842
Abstract: Systems and methods in accordance with various embodiments of the present disclosure provide approaches for mapping entries to a cache using a function, such as cyclic redundancy check (CRC). The function can calculate a colored cache index based on a main memory address. The function may cause consecutive address cache indexes to be spread throughout the cache according to the indexes calculated by the function. In some embodiments, each data context may be associated with a different function, enabling different types of packets to be processed while sharing the same cache, reducing evictions of other data contexts and improving performance. Various embodiments can identify a type of packet as the packet is received, and lookup a mapping function based on the type of packet. The function can then be used to lookup the corresponding data context for the packet from the cache, for processing the packet.
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公开(公告)号:US10298496B1
公开(公告)日:2019-05-21
申请号:US15716036
申请日:2017-09-26
Applicant: Amazon Technologies, Inc.
Inventor: Guy Nakibly , Benzi Denkberg , Erez Izenberg , Nafea Bshara , Uri Leder , Ofer Frishman
IPC: H04L12/747 , H04L12/861 , G06F12/0802 , H04L29/06 , H04L12/931
Abstract: A data or packet processing device such as a network interface controller may include cache control logic that is configured to receive a first request for processing a first data packet associated with the queue identifier, and obtain a set of memory descriptors associated with the queue identifier from the memory. The set of descriptors can be stored in the cache. When a second request for processing a second data packet associated with the queue identifier is received, the cache control logic can determine that the cache is storing memory descriptors for processing the second data packet, and provide the memory descriptors used for processing the second packet.
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公开(公告)号:US10228869B1
公开(公告)日:2019-03-12
申请号:US15716010
申请日:2017-09-26
Applicant: Amazon Technologies, Inc.
Inventor: Guy Nakibly , Benzi Denkberg , Ofer Frishman , Erez Izenberg , Uri Leder , Nafea Bshara
IPC: G06F9/48 , G06F3/06 , H04L12/911 , G06F9/50 , H04L29/08
Abstract: Techniques for controlling access to shared resources may include receiving multiple requests to access shared information associated with an identifier. For each of the requests, an entry in a linked list can be allocated to the request, and each entry can be associated with the identifier. The shared information associated with the identifier can be retrieved, and stored in each entry associated with the identifier. A conflict indicator is set in each entry to indicate whether the shared information is available for the request corresponding to the entry. The shared information stored in each entry is provided for each request after the conflict indicator in the corresponding entry indicates the shared information is available for the request.
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公开(公告)号:US10177795B1
公开(公告)日:2019-01-08
申请号:US15394635
申请日:2016-12-29
Applicant: Amazon Technologies, Inc.
Inventor: Ofer Frishman , Erez Izenberg , Guy Nakibly
Abstract: Systems and methods in accordance with various embodiments of the present disclosure provide approaches for mapping entries to a cache using a function, such as cyclic redundancy check (CRC). The function can calculate a colored cache index based on a main memory address. The function may cause consecutive address cache indexes to be spread throughout the cache according to the indexes calculated by the function. In some embodiments, each data context may be associated with a different function, enabling different types of packets to be processed while sharing the same cache, reducing evictions of other data contexts and improving performance. Various embodiments can identify a type of packet as the packet is received, and lookup a mapping function based on the type of packet. The function can then be used to lookup the corresponding data context for the packet from the cache, for processing the packet.
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