公开(公告)号：US10298496B1

公开(公告)日：2019-05-21

申请号：US15716036

申请日：2017-09-26

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Benzi Denkberg ,  Erez Izenberg ,  Nafea Bshara ,  Uri Leder ,  Ofer Frishman

IPC: H04L12/747 ,  H04L12/861 ,  G06F12/0802 ,  H04L29/06 ,  H04L12/931

Abstract: A data or packet processing device such as a network interface controller may include cache control logic that is configured to receive a first request for processing a first data packet associated with the queue identifier, and obtain a set of memory descriptors associated with the queue identifier from the memory. The set of descriptors can be stored in the cache. When a second request for processing a second data packet associated with the queue identifier is received, the cache control logic can determine that the cache is storing memory descriptors for processing the second data packet, and provide the memory descriptors used for processing the second packet.

公开(公告)号：US11768990B1

公开(公告)日：2023-09-26

申请号：US17305043

申请日：2021-06-29

Applicant: Amazon Technologies, Inc.

Inventor： Uri Leder ,  Ori Ariel ,  Max Chvalevsky ,  Benzi Denkberg ,  Guy Nakibly

IPC: G06F30/398 ,  G06F30/394 ,  G06F30/331 ,  G06F30/392

CPC classification number: G06F30/394 ,  G06F30/331 ,  G06F30/392 ,  G06F30/398

Abstract: An integrated circuit design technique utilizes a data structure describing the connections, interconnect routing information of the connections, and bandwidth requirements of the connections in an integrated circuit device to generate an interconnect flow graph having nodes, and edges connecting the nodes. The edges connecting the nodes can reflect the bandwidth requirements of the connections. The interconnect flow graph can be used to optimize and verify the integrated circuit design.

公开(公告)号：US11544436B1

公开(公告)日：2023-01-03

申请号：US17353715

申请日：2021-06-21

Applicant: Amazon Technologies, Inc.

Inventor： Uri Leder ,  Ori Cohen ,  Benzi Denkberg ,  Max Chvalevsky

IPC: G06F30/3323 ,  G01R31/317 ,  G06F30/31 ,  G06F117/08

Abstract: Hardware-software interaction testing is performed using formal verification for language-specified hardware designs. A description of valid access using an interface for a configuration space of a language specified hardware design and a description of a valid output of the language-specified hardware design is received. Formal verification is performed on the language-specified hardware design using the interface for the configuration space according to the description of valid access using the interface. A sequence of access to the configuration space using the interface that causes a failure to produce the valid output of the language-specified hardware design according to the description of valid output to identify as an error for the language-specified hardware design.

公开(公告)号：US10911358B1

公开(公告)日：2021-02-02

申请号：US16384745

申请日：2019-04-15

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Benzi Denkberg ,  Erez Izenberg ,  Nafea Bshara ,  Uri Leder ,  Ofer Frishman

IPC: H04L12/747 ,  G06F12/0802 ,  H04L12/861 ,  H04L12/931 ,  H04L29/06

Abstract: A data or packet processing device such as a network interface controller may include cache control logic that is configured to obtain a set of memory descriptors associated with a queue from the memory. The set of descriptors can be stored in the cache. When a request for processing a data packet associated with the queue is received, the cache control logic can determine that the cache is storing memory descriptors for processing the data packet, and provide the memory descriptors used for processing the packet.

公开(公告)号：US10929584B1

公开(公告)日：2021-02-23

申请号：US16712933

申请日：2019-12-12

Applicant: Amazon Technologies, Inc.

Inventor： Benzi Denkberg ,  Uri Leder ,  Ori Weber

IPC: G06F30/33 ,  G06F5/06 ,  G06F30/3323

Abstract: Environmental modification testing with a formal verification is implemented for language-specified hardware designs. A language-specified hardware design may be received. A reference copy of the language-specified hardware design may be created. A formal verification may be performed on both the language-specified hardware design and the reference copy with a same input data. Different environmental assumptions for processing the same input data through the reference copy and the language-specified hardware design may be applied. An output value of the language-specified hardware design may be compared with an output value of the reference copy to determine whether those output values match. Error indications may be provided based on a result of the comparison.

公开(公告)号：US10228869B1

公开(公告)日：2019-03-12

申请号：US15716010

申请日：2017-09-26

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Benzi Denkberg ,  Ofer Frishman ,  Erez Izenberg ,  Uri Leder ,  Nafea Bshara

IPC: G06F9/48 ,  G06F3/06 ,  H04L12/911 ,  G06F9/50 ,  H04L29/08

Abstract: Techniques for controlling access to shared resources may include receiving multiple requests to access shared information associated with an identifier. For each of the requests, an entry in a linked list can be allocated to the request, and each entry can be associated with the identifier. The shared information associated with the identifier can be retrieved, and stored in each entry associated with the identifier. A conflict indicator is set in each entry to indicate whether the shared information is available for the request corresponding to the entry. The shared information stored in each entry is provided for each request after the conflict indicator in the corresponding entry indicates the shared information is available for the request.