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公开(公告)号：US08176447B2
公开(公告)日：2012-05-08
申请号：US12791942
申请日：2010-06-02
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method of forming a mask. The method includes providing design information of a design layer. The design layer includes M original design features and N original dummy features. The method further includes (i) creating a cluster of P representative dummy features, P being a positive integer less than N, (ii) performing OPC for the cluster of the P representative dummy features but not for the N original dummy features, resulting in P OPC-applied representative dummy features, and (iii) forming the mask including N mask dummy features. The N mask dummy features are identical. Each mask dummy feature of the N mask dummy features of the mask has an area which is a function of at least an area of an OPC-applied representative dummy feature of the P OPC-applied representative dummy features. The N mask dummy features have the same relative positions as the N original dummy features.
摘要翻译： 一种形成掩模的方法。 该方法包括提供设计层的设计信息。 设计层包括M原始设计特征和N个原始虚拟特征。 该方法还包括（i）创建P代表虚拟特征的聚类，P是小于N的正整数，（ii）对P代表虚拟特征的簇进行OPC，而不对N个原始伪特征执行OPC，导致 P OPC应用的代表虚拟特征，以及（iii）形成包括N个掩模虚拟特征的掩模。 N个掩码虚拟特征是相同的。 掩模的N个掩模虚拟特征的每个掩码虚拟特征具有至少是应用于P OPC应用的代表虚拟特征的OPC应用的代表性虚拟特征的区域的函数的区域。 N个掩模虚拟特征具有与N个原始虚拟特征相同的相对位置。
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公开(公告)号：US20100242012A1
公开(公告)日：2010-09-23
申请号：US12791942
申请日：2010-06-02
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method of forming a mask. The method includes providing design information of a design layer. The design layer includes M original design features and N original dummy features. The method further includes (i) creating a cluster of P representative dummy features, P being a positive integer less than N, (ii) performing OPC for the cluster of the P representative dummy features but not for the N original dummy features, resulting in P OPC-applied representative dummy features, and (iii) forming the mask including N mask dummy features. The N mask dummy features are identical. Each mask dummy feature of the N mask dummy features of the mask has an area which is a function of at least an area of an OPC-applied representative dummy feature of the P OPC-applied representative dummy features. The N mask dummy features have the same relative positions as the N original dummy features.
摘要翻译： 一种形成掩模的方法。 该方法包括提供设计层的设计信息。 设计层包括M原始设计特征和N个原始虚拟特征。 该方法还包括（i）创建P代表虚拟特征的聚类，P是小于N的正整数，（ii）对P代表虚拟特征的簇进行OPC，而不对N个原始伪特征执行OPC，导致 P OPC应用的代表虚拟特征，以及（iii）形成包括N个掩模虚拟特征的掩模。 N个掩码虚拟特征是相同的。 掩模的N个掩模虚拟特征的每个掩码虚拟特征具有至少是应用于P OPC应用的代表虚拟特征的OPC应用的代表性虚拟特征的区域的函数的区域。 N个掩模虚拟特征具有与N个原始虚拟特征相同的相对位置。
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公开(公告)号：US07739648B2
公开(公告)日：2010-06-15
申请号：US11673611
申请日：2007-02-12
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Structures and methods for forming the same. The method includes providing design information of a design layer. The design layer includes M original design features and N original dummy features. The method further includes (i) creating a cluster of P representative dummy features, P being a positive integer less than N, (ii) performing OPC for the cluster of the P representative dummy features but not for the N original dummy features, resulting in P OPC-applied representative dummy features, and (iii) forming the mask including N mask dummy features. The N mask dummy features are identical. Each mask dummy feature of the N mask dummy features of the mask has an area which is a function of at least an area of an OPC-applied representative dummy feature of the P OPC-applied representative dummy features. The N mask dummy features have the same relative positions as the N original dummy features.
摘要翻译： 用于形成它的结构和方法。 该方法包括提供设计层的设计信息。 设计层包括M原始设计特征和N个原始虚拟特征。 该方法还包括（i）创建P代表虚拟特征的聚类，P是小于N的正整数，（ii）对于P代表虚拟特征的簇执行OPC，而不对N个原始伪特征执行OPC，导致 P OPC应用的代表虚拟特征，以及（iii）形成包括N个掩模虚拟特征的掩模。 N个掩码虚拟特征是相同的。 掩模的N个掩模虚拟特征的每个掩码虚拟特征具有至少是应用于P OPC的代表虚拟特征的OPC应用的代表性虚拟特征的区域的函数的面积。 N个掩模虚拟特征具有与N个原始虚拟特征相同的相对位置。
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公开(公告)号：US20080195995A1
公开(公告)日：2008-08-14
申请号：US11673611
申请日：2007-02-12
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Structures and methods for forming the same. The method includes providing design information of a design layer. The design layer includes M original design features and N original dummy features. The method further includes (i) creating a cluster of P representative dummy features, P being a positive integer less than N, (ii) performing OPC for the cluster of the P representative dummy features but not for the N original dummy features, resulting in P OPC-applied representative dummy features, and (iii) forming the mask including N mask dummy features. The N mask dummy features are identical. Each mask dummy feature of the N mask dummy features of the mask has an area which is a function of at least an area of an OPC-applied representative dummy feature of the P OPC-applied representative dummy features. The N mask dummy features have the same relative positions as the N original dummy features.
摘要翻译： 用于形成它的结构和方法。 该方法包括提供设计层的设计信息。 设计层包括M原始设计特征和N个原始虚拟特征。 该方法还包括（i）创建P代表虚拟特征的聚类，P是小于N的正整数，（ii）对P代表虚拟特征的簇进行OPC，而不对N个原始伪特征执行OPC，导致 P OPC应用的代表虚拟特征，以及（iii）形成包括N个掩模虚拟特征的掩模。 N个掩码虚拟特征是相同的。 掩模的N个掩模虚拟特征的每个掩码虚拟特征具有至少是应用于P OPC应用的代表虚拟特征的OPC应用的代表性虚拟特征的区域的函数的区域。 N个掩模虚拟特征具有与N个原始虚拟特征相同的相对位置。
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5.发明授权Automated generation of oxide pillar slot shapes in silicon-on-insulator formation technology 有权在硅绝缘体形成技术中自动生成氧化物柱槽形状公开(公告)号：US08438509B2
公开(公告)日：2013-05-07
申请号：US12621564
申请日：2009-11-19
申请人： William K. Hensen , Michael D. Hulvey , Amit Kumar , Jeanne-Tania Sucharitaves , Amanda L. Tessier
发明人： William K. Hensen , Michael D. Hulvey , Amit Kumar , Jeanne-Tania Sucharitaves , Amanda L. Tessier
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , H01L27/0207 , Y02P90/265
摘要： A method of automated generation of oxide pillar (PX) slot shapes of a PX layer within silicon-on-insulator (SOI) structures that includes generating a placement grid on recess oxide (RX) shapes, creating PX placement markers on the placement grid along a perimeter of the RX shapes, filtering the PX placement markers, generating a PX slot shape corresponding to each filtered PX placement marker on the RX shapes, correcting location errors associated with the generated PX slot shapes, generating PX slot shapes on RX shapes of a predetermined size for which PX slot shapes were not generated, performing a verification operation of the PX slot shapes, and outputting the PX layer including the verified PX slot shapes.
摘要翻译： 在绝缘体上硅（SOI）结构中自动生成PX层的氧化物柱（PX）槽形状的方法，其包括在凹陷氧化物（RX）形状上产生放置栅格，在放置栅格上产生PX放置标记 RX形状的周边，对PX位置标记进行滤波，产生与RX形状上的每个滤波PX放置标记相对应的PX槽形状，校正与所产生的PX槽形状相关联的位置误差，在RX形状上产生PX槽形状 不产生PX槽形状的预定尺寸，执行PX槽形状的验证操作，并输出包括验证的PX槽形状的PX层。
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6.发明申请Automated Generation of Oxide Pillar Slot Shapes in Silicon-On-Insulator Formation Technology 有权硅绝缘体形成技术中自动生成氧化物柱状槽形状公开(公告)号：US20100269085A1
公开(公告)日：2010-10-21
申请号：US12621564
申请日：2009-11-19
申请人： William Kirklen Henson , Michael D. Hulvey , Amit Kumar , Jeanne-Tania Sucharitaves , Amanda L. Tessier
发明人： William Kirklen Henson , Michael D. Hulvey , Amit Kumar , Jeanne-Tania Sucharitaves , Amanda L. Tessier
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , H01L27/0207 , Y02P90/265
摘要： A method of automated generation of oxide pillar (PX) slot shapes of a PX layer within silicon-on-insulator (SOI) structures that includes generating a placement grid on recess oxide (RX) shapes, creating PX placement markers on the placement grid along a perimeter of the RX shapes, filtering the PX placement markers, generating a PX slot shape corresponding to each filtered PX placement marker on the RX shapes, correcting location errors associated with the generated PX slot shapes, generating PX slot shapes on RX shapes of a predetermined size for which PX slot shapes were not generated, performing a verification operation of the PX slot shapes, and outputting the PX layer including the verified PX slot shapes.
摘要翻译： 在绝缘体上硅（SOI）结构中自动生成PX层的氧化物柱（PX）槽形状的方法，其包括在凹陷氧化物（RX）形状上产生放置栅格，在放置栅格上产生PX放置标记 RX形状的周边，对PX位置标记进行滤波，产生与RX形状上的每个滤波PX放置标记相对应的PX槽形状，校正与所产生的PX槽形状相关联的位置误差，在RX形状上产生PX槽形状 不产生PX槽形状的预定尺寸，执行PX槽形状的验证操作，并输出包括验证的PX槽形状的PX层。
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7.发明授权IC chip and design structure including stitched circuitry region boundary identification 有权IC芯片和设计结构包括缝合电路区域边界识别公开(公告)号：US08006211B2
公开(公告)日：2011-08-23
申请号：US12112336
申请日：2008-04-30
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F1/00 , G03F1/50 , G03F7/70466
摘要： Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.
摘要翻译： 针对IC芯片布线的缝合电路区域边界识别以及相关的IC芯片和设计结构。 一种方法包括获得超过光刻工具领域的尺寸的集成电路（IC）芯片布局的电路设计，其中IC芯片布局包括缝合电路区域; 以及修改IC芯片布局以包括标识发生缝合的缝合电路区域的边界的边界标识，其中边界识别在IC芯片布局中采取负空间的形式。 一个IC芯片可以包括多个缝合电路区域; 以及识别一对缝合电路区域之间的边界的边界识别，其中边界识别在IC芯片的层中采取负空间的形式。
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8.发明授权Stitched circuitry region boundary identification for stitched IC chip layout 有权缝合IC芯片布局的缝合电路区域边界识别公开(公告)号：US07958482B2
公开(公告)日：2011-06-07
申请号：US12112329
申请日：2008-04-30
IPC分类号： G06F17/50
CPC分类号： G03F7/70475
摘要： Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.
摘要翻译： 针对IC芯片布线的缝合电路区域边界识别以及相关的IC芯片和设计结构。 一种方法包括获得超过光刻工具领域的尺寸的集成电路（IC）芯片布局的电路设计，其中IC芯片布局包括缝合电路区域; 以及修改IC芯片布局以包括标识发生缝合的缝合电路区域的边界的边界标识，其中边界识别在IC芯片布局中采取负空间的形式。 一个IC芯片可以包括多个缝合电路区域; 以及识别一对缝合电路区域之间的边界的边界识别，其中边界识别在IC芯片的层中采取负空间的形式。
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9.发明授权Structure for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks 有权用于具有交替相移掩模的减少掩模偏置的分割虚拟填充形状的结构公开(公告)号：US07861208B2
公开(公告)日：2010-12-28
申请号：US11872924
申请日：2007-10-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A design structure, method, and system for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks, or with other two-mask lithographic processes employing a trim mask. A design structure is embodied in a machine readable medium used in a design process, the design structure comprising regions in a finished semiconductor design that do not contain as-designed shapes. The design structure additionally includes dummy fill shapes in the regions at a predetermined final density, wherein the generated dummy shapes are sized so that their local density is increased to a predetermined value. Moreover, corresponding trim shapes act to expose an oversized portion of the dummy shape, effectively trimming each dummy shape back to the predetermined final density.
摘要翻译： 用于分割的虚拟填充形状的设计结构，方法和系统，用于减少具有交替相移掩模的掩模偏置，或者使用采用修剪掩模的其它双掩模光刻工艺。 设计结构体现在在设计过程中使用的机器可读介质中，该设计结构包括成品半导体设计中不包含设计形状的区域。 该设计结构还包括在预定最终密度的区域中的虚拟填充形状，其中所生成的虚拟形状的尺寸使得它们的局部密度增加到预定值。 此外，相应的修整形状用于暴露虚拟形状的超大部分，有效地将每个虚拟形状修剪回到预定的最终密度。
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10.发明申请公开(公告)号：US20080072203A1
公开(公告)日：2008-03-20
申请号：US11926567
申请日：2007-10-29
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F2217/72
摘要： A system and method to optimize a circuit layout, and more particularly, to a system and method of post layout data preparation to optimize a circuit layout and reduce random and systematic wire and via opens and shorts. The method includes stripping existing vias in a design layout and determining design parameters of the design layout including wiring placement and dimensions. The method further includes optimizing via layout by placing vias away from edges of the wiring and adjacent vias. The invention is also directed to a design structure on which a circuit resides.
摘要翻译： 一种用于优化电路布局的系统和方法，更具体地，涉及一种用于优化电路布局并减少随机和系统电线以及经由开路和短路的布局布局数据准备的系统和方法。 该方法包括在设计布局中剥离现有的通孔，并确定设计布局的设计参数，包括布线布局和尺寸。 该方法还包括通过将通孔放置在远离布线和相邻通孔的边缘的情况下优化通孔布局。 本发明还涉及电路所在的设计结构。
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