公开(公告)号：US09323678B2

公开(公告)日：2016-04-26

申请号：US13993376

申请日：2011-12-30

Applicant: Amit Kumar ,  Sreenivas Subramoney

Inventor： Amit Kumar ,  Sreenivas Subramoney

IPC: G06F12/08 ,  G06F13/14 ,  G06F9/38

CPC classification number: G06F12/084 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3857 ,  G06F13/14

Abstract: In one embodiment, the present invention includes a method for identifying a memory request corresponding to a load instruction as a critical transaction if an instruction pointer of the load instruction is present in a critical instruction table associated with a processor core, sending the memory request to a system agent of the processor with a critical indicator to identify the memory request as a critical transaction, and prioritizing the memory request ahead of other pending transactions responsive to the critical indicator. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于将与加载指令相对应的存储器请求识别为关键事务的方法，如果加载指令的指令指针存在于与处理器核心相关联的关键指令表中，则将存储器请求发送到 所述处理器的系统代理具有关键指示符以将所述存储器请求识别为关键事务，以及响应于所述关键指示符在其他待处理事务之前优先处理所述存储器请求。 描述和要求保护其他实施例。

公开(公告)号：US20130339595A1

公开(公告)日：2013-12-19

申请号：US13993376

申请日：2011-12-30

Applicant: Amit Kumar ,  Sreenivas Subramoney

Inventor： Amit Kumar ,  Sreenivas Subramoney

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3857 ,  G06F13/14

Abstract: In one embodiment, the present invention includes a method for identifying a memory request corresponding to a load instruction as a critical transaction if an instruction pointer of the load instruction is present in a critical instruction table associated with a processor core, sending the memory request to a system agent of the processor with a critical indicator to identify the memory request as a critical transaction, and prioritizing the memory request ahead of other pending transactions responsive to the critical indicator. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于将与加载指令相对应的存储器请求识别为关键事务的方法，如果加载指令的指令指针存在于与处理器核心相关联的关键指令表中，则将存储器请求发送到 所述处理器的系统代理具有关键指示符以将所述存储器请求识别为关键事务，以及响应于所述关键指示符在其他待处理事务之前优先处理所述存储器请求。 描述和要求保护其他实施例。

公开(公告)号：US07197521B2

公开(公告)日：2007-03-27

申请号：US10719443

申请日：2003-11-21

Applicant: Sreenivas Subramoney ,  Richard Hudson

Inventor： Sreenivas Subramoney ,  Richard Hudson

IPC: G06F17/30 ,  G06F17/00 ,  G06F9/45 ,  G06F12/00

CPC classification number: G06F12/0269 ,  Y10S707/99944 ,  Y10S707/99957

Abstract: An arrangement is provided for using bit vector toggling to achieve concurrent mark-sweep garbage collection in a managed runtime system. A heap may be divided into a number of heap blocks. Each heap block may contain a mark bit vector pointer, a sweep bit vector pointer, and two bit vectors of which one may be initially pointed to by the mark bit vector pointer and used for marking and the other may be initially pointed to by the sweep bit vector pointer and used for sweeping. At the end of the marking phase for a heap block, the bit vector used for marking and the bit vector used for sweeping may be toggled so that marking phase and sweeping phase may proceed concurrently and both phases may proceed concurrently with mutators.

Abstract translation: 提供了一种使用位向量切换在托管运行时系统中实现同时标记扫描垃圾收集的布置。 堆可以分为多个堆块。 每个堆块可以包含标记位向量指针，扫描位矢量指针和两个位向量，其中可以由标记位向量指针最初指向并用于标记的两个位向量，另一个可以由扫描开始指向 位向量指针并用于扫描。 在堆块的标记阶段结束时，可以切换用于标记的位向量和用于扫描的位向量，以便同时进行标记相位和扫描阶段，并且两个阶段可以与变异器同时进行。

公开(公告)号：US06662274B2

公开(公告)日：2003-12-09

申请号：US09886068

申请日：2001-06-20

Applicant: Sreenivas Subramoney ,  Richard L. Hudson

Inventor： Sreenivas Subramoney ,  Richard L. Hudson

IPC: G06F1202

CPC classification number: G06F12/0862 ,  G06F12/0253 ,  G06F2212/6028 ,  Y10S707/99953 ,  Y10S707/99957

Abstract: A method for creating a mark stack for use in a moving garbage collection algorithm is described. The algorithm of the present invention creates a mark stack to implement a MGCA. The algorithm allows efficient use of cache memory prefetch features to reduce the required time to complete the mark stack and thus reduce the time required for garbage collection. Instructions are issued to prefetch data objects that will be examined in the future, so that by the time the scan pointer reaches the data object, the cache lines for the data object are already filled. At some point after the data object is prefetched, the address location of associated data objects is likewise prefetched. Finally, the associated data objects located at the previously fetched addresses are prefetched. This reduces garbage collection by continually supplying the garbage collector with a stream of preemptively prefetched data objects that require scanning.

公开(公告)号：US20210232312A1

公开(公告)日：2021-07-29

申请号：US17214534

申请日：2021-03-26

Applicant: Aravinda Prasad ,  Sandeep Kumar ,  Sreenivas Subramoney ,  Andy Rudoff

Inventor： Aravinda Prasad ,  Sandeep Kumar ,  Sreenivas Subramoney ,  Andy Rudoff

IPC: G06F3/06

Abstract: Disclosed Methods, Apparatus, and articles of manufacture to profile page tables for memory management are disclosed. An example apparatus includes a processor to execute computer readable instructions to: profile a first page at a first level of a page table as not part of a target group; and in response to profiling the first page as not part of the target group, label a data page at a second level that corresponds to the first page as not part of the target group, the second level being lower than the first level.

公开(公告)号：US20140368524A1

公开(公告)日：2014-12-18

申请号：US13993811

申请日：2011-12-29

Applicant: Suresh Srinivasan ,  Ramesh K. Rakesh ,  Sreenivas Subramoney ,  Jayesh Gaur

Inventor： Suresh Srinivasan ,  Ramesh K. Rakesh ,  Sreenivas Subramoney ,  Jayesh Gaur

IPC: G06F12/08 ,  G06T1/60

CPC classification number: G06F12/0802 ,  G06F12/0888 ,  G06T1/60 ,  G06T2200/28

Abstract: Some implementations disclosed herein provide techniques for caching memory data and for managing cache retention. Different cache retention policies may be applied to different cached data streams such as those of a graphics processing unit. Actual performance of the cache with respect to the data streams may be observed, and the cache retention policies may be varied based on the observed actual performance.

Abstract translation: 本文中公开的一些实施例提供了用于缓存存储器数据和用于管理高速缓存保留的技术。 不同的缓存保留策略可以应用于不同的缓存数据流，例如图形处理单元的缓存数据流。 可以观察到相对于数据流的缓存的实际性能，并且可以基于所观察的实际性能来改变高速缓存保留策略。

公开(公告)号：US20250004766A1

公开(公告)日：2025-01-02

申请号：US18759331

申请日：2024-06-28

Applicant: Jayesh Gaur ,  Sumeet Bandishte ,  Anant Nori ,  Michael Chynoweth ,  Sreenivas Subramoney ,  Adi Yoaz ,  Anshuman Dhuliya

Inventor： Jayesh Gaur ,  Sumeet Bandishte ,  Anant Nori ,  Michael Chynoweth ,  Sreenivas Subramoney ,  Adi Yoaz ,  Anshuman Dhuliya

IPC: G06F9/30

Abstract: Techniques for software defined super core usage are described. In some examples, a first and a second processor core are to operate as a single virtual core as configured by the operating system to execute the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently using a shared memory space, wherein the instruction segments are to include one or more of a store instruction to store live register data to be shared with another core and a load instruction to load live register data shared by another core.

公开(公告)号：US20160179387A1

公开(公告)日：2016-06-23

申请号：US14971057

申请日：2015-12-16

Applicant: Jayesh Gaur ,  Prasanna Rengasamy ,  Pradeep Ramachandran ,  Sreenivas Subramoney

Inventor： Jayesh Gaur ,  Prasanna Rengasamy ,  Pradeep Ramachandran ,  Sreenivas Subramoney

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0604 ,  G06F3/0613 ,  G06F3/0653 ,  G06F3/0671 ,  G06F12/0888

Abstract: A processor includes an execution unit, a memory subsystem, and a memory management unit (MMU). The MMU includes logic to evaluate a first bandwidth usage of the memory subsystem and logic to evaluate a second bandwidth usage between the processor and a memory. The memory is communicatively coupled to the memory subsystem. The memory subsystem is to implement a cache for the memory. The MMU further includes logic to evaluate a request of the memory subsystem, and, based upon the first bandwidth usage and the second bandwidth usage, fulfill the request by bypassing the memory subsystem.

Abstract translation: 处理器包括执行单元，存储器子系统和存储器管理单元（MMU）。 MMU包括评估存储器子系统的第一带宽使用和评估处理器和存储器之间的第二带宽使用的逻辑的逻辑。 存储器通信地耦合到存储器子系统。 内存子系统是为内存实现缓存。 MMU还包括评估存储器子系统的请求的逻辑，并且基于第一带宽使用和第二带宽使用，通过绕过存储器子系统来满足请求。

公开(公告)号：US20130166846A1

公开(公告)日：2013-06-27

申请号：US13722607

申请日：2012-12-20

Applicant: Jayesh Gaur ,  Mainak Chaudhuri ,  Sreenivas Subramoney ,  Nithiyanandan Bashyam ,  Joseph Nuzman

Inventor： Jayesh Gaur ,  Mainak Chaudhuri ,  Sreenivas Subramoney ,  Nithiyanandan Bashyam ,  Joseph Nuzman

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0897 ,  G06F12/128

Abstract: Some implementations disclosed herein provide techniques and arrangements for a hierarchy-aware replacement policy for a last-level cache. A detector may be used to provide the last-level cache with information about blocks in a lower-level cache. For example, the detector may receive a notification identifying a block evicted from the lower-level cache. The notification may include a category associated with the block. The detector may identify a request that caused the block to be filled into the lower-level cache. The detector may determine whether one or more statistics associated with the category satisfy a threshold. In response to determining that the one or more statistics associated with the category satisfy the threshold, the detector may send an indication to the last-level cache that the block is a candidate for eviction from the last-level cache.

Abstract translation: 本文中公开的一些实施例提供了用于最后一级高速缓存的层次感知替换策略的技术和布置。 可以使用检测器来向最后一级缓存提供关于下级缓存中的块的信息。 例如，检测器可以接收识别从下级缓存中移出的块的通知。 通知可以包括与块相关联的类别。 检测器可以识别导致块被填充到下级高速缓存中的请求。 检测器可以确定与该类别相关联的一个或多个统计信息是否满足阈值。 响应于确定与类别相关联的一个或多个统计信息满足阈值，检测器可以向最后一级高速缓存发送指示该块是从最后一级高速缓存撤出的候选者的指示。

公开(公告)号：US07389385B2

公开(公告)日：2008-06-17

申请号：US10742009

申请日：2003-12-19

Applicant: Mauricio J. Serrano ,  Sreenivas Subramoney ,  Richard L. Hudson ,  Ali-Reza Adl-Tabatabai

Inventor： Mauricio J. Serrano ,  Sreenivas Subramoney ,  Richard L. Hudson ,  Ali-Reza Adl-Tabatabai

IPC: G06F12/00 ,  G06F9/26 ,  G06F9/45 ,  G06F11/30

CPC classification number: G06F12/0253

Abstract: Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with cache misses from a performance monitoring unit in a processor system are received. One or more samples from the one or more batches of samples based on delinquent information are selected. A performance impact indicator associated with the one or more samples is generated. Based on the performance indicator, at least one of a garbage collector analysis and a compiler analysis is initiated to identify one or more delinquent paths. Based on the at least one of the garbage collector analysis and the compiler analysis, one or more prefetch points to insert prefetch instructions are identified.

Abstract translation: 公开了基于垃圾收集器分析和编译器分析来插入预取指令的方法和装置。 在示例性方法中，接收与处理器系统中的来自性能监视单元的高速缓存未命中关联的一个或多个批次的样本。 选择一个或多个基于犯罪信息的样本的一个或多个样本。 产生与一个或多个样本相关联的性能影响指示符。 基于性能指标，启动垃圾回收器分析和编译器分析中的至少一个以识别一个或多个违规路径。 基于垃圾收集器分析和编译器分析中的至少一个，识别插入预取指令的一个或多个预取点。