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公开(公告)号：US11876039B2
公开(公告)日：2024-01-16
申请号：US17838200
申请日：2022-06-11
IPC分类号： H01L23/498 , H01L25/00 , H01L25/065 , H01L25/18 , H01L23/00 , H01L21/48 , H01L21/56 , H01L23/31
CPC分类号： H01L23/49816 , H01L21/4853 , H01L21/56 , H01L23/3185 , H01L23/49822 , H01L24/11 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/73253
摘要： In one example, a semiconductor device includes a substrate with a top side, a bottom side, and a conductive structure. A first electronic component includes a first side, a second side, and first component terminals adjacent to the first side. The first component terminals face the substrate bottom side and are connected to the conductive structure. A second electronic component comprises a first side, a second side, and second component terminals adjacent to the second electronic component first side. The second electronic component second side is connected to the first electronic component second side with a coupling structure so that the first component terminals and the second component terminals face opposite directions. Interconnects are connected to the conductive structure. The second component terminals and the interconnects are configured for connecting to a next level assembly. Other examples and related methods are also disclosed herein.
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公开(公告)号：US20210111151A1
公开(公告)日：2021-04-15
申请号：US17080038
申请日：2020-10-26
IPC分类号： H01L23/00 , H01L23/31 , H01L23/12 , H01L23/498 , H01L21/56
摘要： Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.
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公开(公告)号：US11362027B2
公开(公告)日：2022-06-14
申请号：US16805027
申请日：2020-02-28
IPC分类号： H01L23/498 , H01L25/00 , H01L25/065 , H01L25/18 , H01L23/00 , H01L21/48 , H01L21/56 , H01L23/31
摘要： In one example, a semiconductor device includes a substrate with a top side, a bottom side, and a conductive structure. A first electronic component includes a first side, a second side, and first component terminals adjacent to the first side. The first component terminals face the substrate bottom side and are connected to the conductive structure. A second electronic component comprises a first side, a second side, and second component terminals adjacent to the second electronic component first side. The second electronic component second side is connected to the first electronic component second side so that the first component terminals and the second component terminals face opposite directions. Substrate interconnects are connected to the conductive structure, and a bottom encapsulant covers the substrate bottom side, the first electronic component, the second electronic component, and the substrate interconnects. Portions of the second component terminals and the substrate interconnects are exposed from a bottom side of the bottom encapsulant. Other examples and related methods are also disclosed herein.
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公开(公告)号：US12009343B1
公开(公告)日：2024-06-11
申请号：US15347545
申请日：2016-11-09
IPC分类号： H01L25/065 , H01L21/56 , H01L23/00 , H01L23/31 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/563 , H01L23/3121 , H01L24/11 , H01L24/17 , H01L25/50 , H01L2224/48091 , H01L2225/0651 , H01L2225/0652 , H01L2225/06548 , H01L2225/06589
摘要： A stackable package is placed within a mold during an encapsulation operation. A compliant surface, e.g., of a compliant film, of the mold is pressed down on upper interconnection balls of the stackable package to force upper portions of the upper interconnection balls into the mold. However, lower portions of the upper interconnection balls are exposed within a space between the compliant surface and a substrate of the stackable package. The space is filled with a dielectric material to form a package body. The package body is formed while at the same time exposing the upper portions of upper interconnection balls from the package body in a single encapsulation operation. By avoiding selective removal of the package body to expose the upper interconnection balls, the number of operations as well as cost to manufacture the stackable package is minimized.
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公开(公告)号：US11488892B2
公开(公告)日：2022-11-01
申请号：US16927454
申请日：2020-07-13
发明人： Louis W. Nicholls , Roger D. St. Amand , Jin Seong Kim , Woon Kab Jung , Sung Jin Yang , Robert F. Darveaux
IPC分类号： H01L23/48 , H01L23/498 , H01L21/48 , H01L23/31 , H01L23/538
摘要： A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.
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公开(公告)号：US20210166992A1
公开(公告)日：2021-06-03
申请号：US16927454
申请日：2020-07-13
发明人： Louis W. Nicholls , Roger D. St. Amand , Jin Seong Kim , Woon Kab Jung , Sung Jin Yang , Robert F. Darveaux
IPC分类号： H01L23/48 , H01L23/498 , H01L21/48 , H01L23/31 , H01L23/538
摘要： A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.
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公开(公告)号：US11621243B2
公开(公告)日：2023-04-04
申请号：US17080038
申请日：2020-10-26
IPC分类号： H01L23/00 , H01L23/31 , H01L23/12 , H01L23/498 , H01L21/56 , H01L23/552
摘要： Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.
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公开(公告)号：US20210272887A1
公开(公告)日：2021-09-02
申请号：US16805027
申请日：2020-02-28
IPC分类号： H01L23/498 , H01L25/00 , H01L25/065 , H01L25/18 , H01L23/00 , H01L21/48 , H01L21/56 , H01L23/31
摘要： In one example, a semiconductor device includes a substrate with a top side, a bottom side, and a conductive structure. A first electronic component includes a first side, a second side, and first component terminals adjacent to the first side. The first component terminals face the substrate bottom side and are connected to the conductive structure. A second electronic component comprises a first side, a second side, and second component terminals adjacent to the second electronic component first side. The second electronic component second side is connected to the first electronic component second side so that the first component terminals and the second component terminals face opposite directions. Substrate interconnects are connected to the conductive structure, and a bottom encapsulant covers the substrate bottom side, the first electronic component, the second electronic component, and the substrate interconnects. Portions of the second component terminals and the substrate interconnects are exposed from a bottom side of the bottom encapsulant. Other examples and related methods are also disclosed herein.
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