公开(公告)号：US08798570B2

公开(公告)日：2014-08-05

申请号：US13323103

申请日：2011-12-12

申请人： Amr M. Fahim ,  Stephen A. Jantzi ,  Afshin Mellati

发明人： Amr M. Fahim ,  Stephen A. Jantzi ,  Afshin Mellati

IPC分类号： H04B1/16 ,  H03H11/12 ,  H03H11/46

CPC分类号： H03G3/3052 ,  H04B1/1027

摘要： A receiver, such as a television tuner, includes a radio frequency (RF) filter circuit. The RF filter circuit includes a filter, a first node, and a second node coupled to the filter, and a conversion signal path having an input coupled to the first node and an output coupled to the second node, the conversion signal path having an active mixer coupled between the first node and the second node. The active mixer can include, for example, a first transconductor and a first mixer coupled in series between the first node and the second node. The RF filter circuit further includes a feedback signal path having an input coupled to the second node and an output coupled to the first node, the feedback signal path including a second transconductor and a second mixer coupled in series between the second node and the first node.

摘要翻译： 诸如电视调谐器的接收机包括射频（RF）滤波器电路。 RF滤波器电路包括滤波器，第一节点和耦合到滤波器的第二节点，以及具有耦合到第一节点的输入和耦合到第二节点的输出的转换信号路径，转换信号路径具有活动 耦合在第一节点和第二节点之间的混合器。 有源混频器可以包括例如串联耦合在第一节点和第二节点之间的第一跨导器和第一混频器。 RF滤波器电路还包括具有耦合到第二节点的输入和耦合到第一节点的输出的反馈信号路径，反馈信号路径包括串联耦合在第二节点和第一节点之间的第二跨导器和第二混频器 。

公开(公告)号：US20130149983A1

公开(公告)日：2013-06-13

申请号：US13323103

申请日：2011-12-12

申请人： Amr M. Fahim ,  Stephen A. Jantzi ,  Afshin Mellati

发明人： Amr M. Fahim ,  Stephen A. Jantzi ,  Afshin Mellati

IPC分类号： H04B1/26

CPC分类号： H03G3/3052 ,  H04B1/1027

摘要： A receiver, such as a television tuner, includes a radio frequency (RF) filter circuit. The RF filter circuit includes a filter, a first node, and a second node coupled to the filter, and a conversion signal path having an input coupled to the first node and an output coupled to the second node, the conversion signal path having an active mixer coupled between the first node and the second node. The active mixer can include, for example, a first transconductor and a first mixer coupled in series between the first node and the second node. The RF filter circuit further includes a feedback signal path having an input coupled to the second node and an output coupled to the first node, the feedback signal path including a second transconductor and a second mixer coupled in series between the second node and the first node.

摘要翻译： 诸如电视调谐器的接收机包括射频（RF）滤波器电路。 RF滤波器电路包括滤波器，第一节点和耦合到滤波器的第二节点，以及具有耦合到第一节点的输入和耦合到第二节点的输出的转换信号路径，转换信号路径具有活动 耦合在第一节点和第二节点之间的混合器。 有源混频器可以包括例如串联耦合在第一节点和第二节点之间的第一跨导器和第一混频器。 RF滤波器电路还包括具有耦合到第二节点的输入和耦合到第一节点的输出的反馈信号路径，反馈信号路径包括串联耦合在第二节点和第一节点之间的第二跨导器和第二混频器 。

公开(公告)号：US08666352B2

公开(公告)日：2014-03-04

申请号：US13327836

申请日：2011-12-16

申请人： Stephen A. Jantzi ,  Amr M. Fahim

发明人： Stephen A. Jantzi ,  Amr M. Fahim

IPC分类号： H04B1/26

CPC分类号： H04B1/3805 ,  H04B1/525

摘要： A radio frequency (RF) receiver, such as a television tuner, includes a harmonic cancellation circuit. The harmonic cancellation circuit includes a primary signal path to generate a first intermediate frequency (IF) signal by mixing an RF signal with a reference signal and a harmonic feedforward signal path to generate a second IF signal representing signal content of the RF signal near an nth-order harmonic of a frequency fLO of the first reference signal, n comprising a positive integer. The harmonic cancellation circuit further includes a summation stage to generate a third IF signal based on a difference between the first IF signal and the second IF signal.

摘要翻译： 诸如电视调谐器的射频（RF）接收机包括谐波消除电路。 谐波消除电路包括通过将RF信号与参考信号和谐波前馈信号路径混合来产生第一中频（IF）信号的主信号路径，以产生表示在第n个附近的RF信号的信号内容的第二IF信号 第一参考信号的频率fLO的顺序谐波，n包括正整数。 谐波消除电路还包括基于第一IF信号和第二IF信号之间的差产生第三IF信号的求和级。

公开(公告)号：US20130157604A1

公开(公告)日：2013-06-20

申请号：US13327836

申请日：2011-12-16

申请人： Stephen A. Jantzi ,  Amr M. Fahim

发明人： Stephen A. Jantzi ,  Amr M. Fahim

IPC分类号： H04B1/10

CPC分类号： H04B1/3805 ,  H04B1/525

摘要： A radio frequency (RF) receiver, such as a television tuner, includes a harmonic cancellation circuit. The harmonic cancellation circuit includes a primary signal path to generate a first intermediate frequency (IF) signal by mixing an RF signal with a reference signal and a harmonic feedforward signal path to generate a second IF signal representing signal content of the RF signal near an nth-order harmonic of a frequency fLO of the first reference signal, n comprising a positive integer. The harmonic cancellation circuit further includes a summation stage to generate a third IF signal based on a difference between the first IF signal and the second IF signal.

摘要翻译： 诸如电视调谐器的射频（RF）接收机包括谐波消除电路。 谐波消除电路包括通过将RF信号与参考信号和谐波前馈信号路径混合来产生第一中频（IF）信号的主信号路径，以产生表示在第n个附近的RF信号的信号内容的第二IF信号 第一参考信号的频率fLO的顺序谐波，n包括正整数。 谐波消除电路还包括基于第一IF信号和第二IF信号之间的差产生第三IF信号的求和级。

公开(公告)号：US07323944B2

公开(公告)日：2008-01-29

申请号：US11103743

申请日：2005-04-11

申请人： Octavian Florescu ,  Amr M. Fahim ,  Chiewcharn Narathong

发明人： Octavian Florescu ,  Amr M. Fahim ,  Chiewcharn Narathong

IPC分类号： H03L7/06 ,  H03L7/10

CPC分类号： H03L7/199 ,  H03L7/0898 ,  H03L7/10

摘要： A PLL includes a charge pump, a loop filter, a VCO, and a calibration unit. The calibration unit performs coarse tuning to select one or multiple frequency ranges, performs fine tuning to determine an initial control voltage that puts the VCO near a desired operating frequency, measures the VCO gain at different control voltages, and derives VCO gain compensation values for the different control voltages. The calibration unit also pre-charges the loop filter to the initial control voltage to shorten acquisition time, enables the loop filter to drive the VCO to lock to the desired operating frequency, and performs VCO gain compensation during normal operation. For VCO gain compensation, the calibration unit measures the control voltage, obtains the VCO gain compensation value for the measured control voltage, and adjusts the gain of at least one circuit block (e.g., the charge pump) to account for variation in the VCO gain.

摘要翻译： PLL包括电荷泵，环路滤波器，VCO和校准单元。 校准单元执行粗调以选择一个或多个频率范围，执行微调以确定将VCO置于所需工作频率附近的初始控制电压，测量不同控制电压下的VCO增益，并导出VCO增益补偿值 不同的控制电压。 校准单元还将环路滤波器预充电到初始控制电压以缩短采集时间，使环路滤波器能够驱动VCO锁定到所需的工作频率，并在正常操作期间执行VCO增益补偿。 对于VCO增益补偿，校准单元测量控制电压，获得测量的控制电压的VCO增益补偿值，并调整至少一个电路块（例如，电荷泵）的增益，以考虑VCO增益的变化 。

公开(公告)号：US07098708B2

公开(公告)日：2006-08-29

申请号：US11186451

申请日：2005-07-20

申请人： Amr M. Fahim

发明人： Amr M. Fahim

IPC分类号： H03L7/06

CPC分类号： G06F1/022 ,  G06F1/08 ,  G06F2211/902 ,  H03K5/135 ,  H03K5/1565 ,  H03K2005/00032 ,  H03K2005/00071 ,  H03L7/0814

摘要： An MN counter with analog interpolation (“MNA counter”) includes an MN counter, a multiplier, a delay generator, and a current generator. The MN counter receives an input clock signal and M and N values, accumulates M for each input clock cycle using a modulo-N accumulator, and provides an accumulator value and a counter signal with the desired frequency. The multiplier multiplies the accumulator value with an inverse of M and provides an L-bit control signal. The current generator implements a current locked loop that provides a reference current for the delay generator. The delay generator is implemented with a differential design, receives the counter signal and the L-bit control signal, compares a differential signal generated based on the counter and control signals, and provides the output clock signal. The leading edges of the output clock signal have variable delay determined by the L-bit control signal and the reference current.

摘要翻译： 具有模拟插值（“MNA计数器”）的MN计数器包括MN计数器，乘法器，延迟发生器和电流发生器。 MN计数器接收输入时钟信号和M和N值，使用模N累加器为每个输入时钟周期累加M，并提供具有所需频率的累加器值和计数器信号。 乘法器将累加器值乘以M的倒数，并提供L位控制信号。 电流发生器实现电流锁定环路，为延迟发生器提供参考电流。 延迟发生器采用差分设计实现，接收计数器信号和L位控制信号，比较基于计数器和控制信号产生的差分信号，并提供输出时钟信号。 输出时钟信号的前沿具有由L位控制信号和参考电流确定的可变延迟。

公开(公告)号：US06958635B2

公开(公告)日：2005-10-25

申请号：US10684797

申请日：2003-10-14

申请人： Amr M. Fahim

发明人： Amr M. Fahim

IPC分类号： G06F1/02 ,  G06F1/08 ,  H03K3/017 ,  H03K5/00 ,  H03K5/135 ,  H03K5/156 ,  H03K23/68 ,  H03L7/081 ,  H03L7/06

CPC分类号： G06F1/022 ,  G06F1/08 ,  G06F2211/902 ,  H03K5/135 ,  H03K5/1565 ,  H03K2005/00032 ,  H03K2005/00071 ,  H03L7/0814

摘要： An MN counter with analog interpolation (an “MNA counter”) includes an MN counter, a multiplier, a delay generator, and a current generator. The MN counter receives an input clock signal and M and N values, accumulates M for each input clock cycle using a modulo-N accumulator, and provides an accumulator value and a counter signal with the desired frequency. The multiplier multiplies the accumulator value with an inverse of M and provides an L-bit control signal. The current generator implements a current locked loop that provides a reference current for the delay generator. The delay generator is implemented with a differential design, receives the counter signal and the L-bit control signal, compares a differential signal generated based on the counter and control signals, and provides the output clock signal. The leading edges of the output clock signal have variable delay determined by the L-bit control signal and the reference current.