公开(公告)号：US20160087780A1

公开(公告)日：2016-03-24

申请号：US14735086

申请日：2015-06-09

Applicant: Analog Devices, Inc.

Inventor： Bikiran Goswami ,  Baoxing Chen

IPC: H04L5/22 ,  H04B15/00

CPC classification number: H04B5/0031 ,  H04B5/005 ,  H04L27/08 ,  H04L47/825

Abstract: An embodiment of a communication system for transmitting and receiving data across an isolation barrier may include a communication circuit connected to an isolator at a first side of the isolation barrier, the communication circuit having a transmit circuit to drive a first data signal onto the isolator based on input data received by the communication circuit, a receive circuit to receive a second data signal from the isolator and produce output data based on the received second data signal, and a control circuit to control the transmit and receive circuits to provide time division multiplexing of the first and second data signals. The control circuit may transition to a transmit state in which the transmit circuit drives the first data signal onto the isolator from a receive state in which the receive circuit receives the second data signal from the isolator in response to detecting a condition as a function of receiving a predetermined number of bits of the second data signal and passage of a predetermined time period.

Abstract translation: 用于在隔离屏障上发送和接收数据的通信系统的实施例可以包括连接到隔离屏障第一侧的隔离器的通信电路，该通信电路具有用于将第一数据信号驱动到隔离器上的发射电路 在由通信电路接收的输入数据上，接收电路接收来自隔离器的第二数据信号，并基于接收到的第二数据信号产生输出数据;以及控制电路，用于控制发射和接收电路，以提供时分复用 第一和第二数据信号。 控制电路可以转变到发射状态，其中发射电路从接收状态驱动第一数据信号到接收状态，其中接收电路响应于检测到作为接收的函数的条件而从隔离器接收第二数据信号 第二数据信号的预定数量的位和经过预定时间段。

公开(公告)号：US20220294672A1

公开(公告)日：2022-09-15

申请号：US17334445

申请日：2021-05-28

Applicant: Analog Devices, Inc.

Inventor： Eric C. Gaalaas ,  Dongwan Ha ,  Jason J. Ziomek ,  Bikiran Goswami ,  Brian Jadus

IPC: H04L25/02

Abstract: Methods and apparatus are disclosed for communicating multiple logic states across a digital isolator. The digital isolator is a universal serial bus (USB) isolator in some embodiments. The digital isolator includes one or more single-bit data channels. Three or more logic states of information are transmitted across the single-bit data channel(s). The logic states are distinguished by a pulse sequence, and in particular a number of edges of the pulse sequence and a final value or final edge of the pulse sequence.

公开(公告)号：US20160087914A1

公开(公告)日：2016-03-24

申请号：US14735104

申请日：2015-06-09

Applicant: Analog Devices, Inc.

Inventor： Bikiran Goswami ,  Baoxing Chen

IPC: H04L12/911 ,  H04B5/00 ,  H04L27/08

CPC classification number: H04B5/0031 ,  H04B5/005 ,  H04L27/08 ,  H04L47/825

Abstract: An embodiment of a communication circuit for communicating data across an isolation barrier may include an input circuit to receive a plurality of input data channels, a framing circuit to frame an input data packet from the plurality of input data channels, an encoding circuit to select a characteristic of a data symbol to represent a plurality of bits of the framed input data packet, and a driver circuit to drive one or more data symbols representing the framed input data packet onto an isolator configured to communicate data across the isolation barrier. The encoding circuit may select an amplitude, frequency or phase of the data symbol from a plurality of predetermined amplitudes, frequencies or phases, to encode the plurality of bits as the selected amplitude, frequency or phase. The communication circuit also may include a receive circuit to receive one or more second data symbols from the isolator, a decoding circuit to decode a plurality of bits of an output data packet as a function of a characteristic of the second data symbol, and a deframing circuit to deframe the output data packet into output data of a plurality of output data channels.

Abstract translation: 用于在隔离屏障上传送数据的通信电路的实施例可以包括：用于接收多个输入数据信道的输入电路，用于对来自多个输入数据信道的输入数据分组进行帧化的成帧电路;编码电路， 用于表示成帧输入数据分组的多个比特的数据符号的特征;以及驱动器电路，用于将表示成帧的输入数据分组的一个或多个数据符号驱动到被配置为跨越隔离屏障传送数据的隔离器。 编码电路可以从多个预定幅度，频率或相位选择数据符号的幅度，频率或相位，以将多个比特编码为所选择的幅度，频率或相位。 通信电路还可以包括接收电路以从隔离器接收一个或多个第二数据符号，解码电路，用于根据第二数据符号的特性来解码输出数据分组的多个比特，以及去帧 电路将输出数据分组解码为多个输出数据信道的输出数据。

公开(公告)号：US11637724B2

公开(公告)日：2023-04-25

申请号：US17334445

申请日：2021-05-28

Applicant: Analog Devices, Inc.

Inventor： Eric C. Gaalaas ,  Dongwan Ha ,  Jason J. Ziomek ,  Bikiran Goswami ,  Brian Jadus

IPC: H04L25/02 ,  H02M3/335

Abstract: Methods and apparatus are disclosed for communicating multiple logic states across a digital isolator. The digital isolator is a universal serial bus (USB) isolator in some embodiments. The digital isolator includes one or more single-bit data channels. Three or more logic states of information are transmitted across the single-bit data channel(s). The logic states are distinguished by a pulse sequence, and in particular a number of edges of the pulse sequence and a final value or final edge of the pulse sequence.

公开(公告)号：US10277278B2

公开(公告)日：2019-04-30

申请号：US14735086

申请日：2015-06-09

Applicant: Analog Devices, Inc.

Inventor： Bikiran Goswami ,  Baoxing Chen

IPC: H04J3/00 ,  H04B5/00 ,  H04L27/08 ,  H04L12/911

Abstract: An embodiment of a communication system for transmitting and receiving data across an isolation barrier may include a communication circuit connected to an isolator at a first side of the isolation barrier, the communication circuit having a transmit circuit to drive a first data signal onto the isolator based on input data received by the communication circuit, a receive circuit to receive a second data signal from the isolator and produce output data based on the received second data signal, and a control circuit to control the transmit and receive circuits to provide time division multiplexing of the first and second data signals. The control circuit may transition to a transmit state in which the transmit circuit drives the first data signal onto the isolator from a receive state in which the receive circuit receives the second data signal from the isolator in response to detecting a condition as a function of receiving a predetermined number of bits of the second data signal and passage of a predetermined time period.