公开(公告)号：US20140145785A1

公开(公告)日：2014-05-29

申请号：US13684904

申请日：2012-11-26

Applicant: ANALOG DEVICES, INC.

Inventor： ABHISHEK BANDYOPADHYAY ,  David Paul FOLEY

IPC: H03F1/34 ,  H03F3/45

CPC classification number: H03F1/34 ,  H03F3/45475 ,  H03F2203/45134 ,  H03F2203/45138 ,  H03F2203/45522 ,  H03F2203/45526

Abstract: Apparatus and methods for equalization are provided. In certain implementations, an equalizer includes first and second feedback resistors, first and second equalization resistors, an equalization capacitor, and an amplification circuit that includes first to fourth input terminals and first and second output terminals. The amplification circuit can receive a differential input voltage signal between the first and third input terminals, and the first and second equalization resistors and the equalization capacitor are electrically connected in series between the second and fourth input terminals with the equalization capacitor between the first and second equalization resistors. Additionally, the first feedback resistor is electrically connected between the first output terminal and the second input terminal, and the second feedback resistor is electrically connected between the second output terminal and the fourth input terminal.

Abstract translation: 提供了用于均衡的装置和方法。 在某些实现中，均衡器包括第一和第二反馈电阻器，第一和第二均衡电阻器，均衡电容器和包括第一至第四输入端子和第一和第二输出端子的放大电路。 放大电路可以在第一和第三输入端子之间接收差分输入电压信号，并且第一和第二均衡电阻器和均衡电容器串联地电连接在第二和第四输入端子之间，均衡电容器在第一和第二输入端子之间 均衡电阻。 此外，第一反馈电阻器电连接在第一输出端子和第二输入端子之间，第二反馈电阻器电连接在第二输出端子和第四输入端子之间。

公开(公告)号：US20170317683A1

公开(公告)日：2017-11-02

申请号：US15583183

申请日：2017-05-01

Applicant: Analog Devices, Inc.

Inventor： ABHISHEK BANDYOPADHYAY ,  Dan BOYKO ,  Eric G. NESTLER

IPC: H03M1/08 ,  H03M1/00

CPC classification number: H03M1/0854 ,  H03M1/002 ,  H03M1/468 ,  H03M3/426 ,  H03M3/458

Abstract: Systems and methods are disclosed for a noise-shaping successive approximation register (SAR) analog-to-digital-converter (ADC) using Sampled Analog Technology (SAT) filter techniques for filter construction. A SAR ADC includes an SAR for receiving an analog input signal and outputting a digital decision, a digital-to-analog converter and logic circuitry for converting the digital decision of the SAR to a present analog residue for a present conversion cycle, a filter for processing a previous analog residue from a previous conversion cycle, and for feeding a processed previous analog residue back to the SAR, a summer for summing the processed previous analog residue from the filter and the present analog residue, and generating a summer output, and a comparator for comparing the summer output and a first reference signal and generating a comparator output. The filter includes a capacitor array for filtering the previous analog residue to generate the processed previous analog residue.

公开(公告)号：US20160359499A1

公开(公告)日：2016-12-08

申请号：US15067847

申请日：2016-03-11

Applicant: ANALOG DEVICES, INC.

Inventor： ABHISHEK BANDYOPADHYAY

IPC: H03M3/00

CPC classification number: H03M3/422 ,  H03M3/30 ,  H03M3/352 ,  H03M3/45 ,  H03M3/454 ,  H03M3/458

Abstract: A modified topology for a CTDSM (referred herein as “SCFF”) can effectively deal with signal transfer function (STF) peaking, an inherent property of continuous time feedforward delta sigma converters. The SCFF approach involves providing an additional digital-to-analog (DAC) feedback path to the input of the second integrator (incurring an additional DAC in the circuitry, converting the output of the quantizer into an analog signal and feeding the analog signal to the input of the second integrator). Furthermore, the SCFF approach involves providing two feed-ins: a first feed-in to the input of the second integrator and a second feed-in to the input of the third integrator. The first feed-in can be negative. Advantageously, the modified continuous time delta sigma modulator implementing this approach alleviates some of the peaking issues in the signal transfer function while still enjoy low power consumption.

Abstract translation: 用于CTDSM（本文称为“SCFF”）的修改拓扑可以有效地处理信号传递函数（STF）峰值，这是连续时间前馈Δ-Σ转换器的固有特性。 SCFF方法包括为第二积分器的输入提供额外的数模（DAC）反馈路径（在电路中产生附加的DAC，将量化器的输出转换为模拟信号，并将模拟信号馈送到 第二积分器的输入）。 此外，SCFF方法包括提供两个馈入：第二积分器的输入的第一馈入和第三积分器的输入的第二馈入。 第一个馈入可以是否定的。 有利地，实现该方法的经修改的连续时间ΔΣ调制器减轻了信号传递功能中的一些峰值问题，同时仍享有低功耗。