公开(公告)号：US10749535B2

公开(公告)日：2020-08-18

申请号：US16011970

申请日：2018-06-19

申请人： Analog Devices, Inc.

发明人： Reuben P. Nelson ,  Neil E. Weeks

IPC分类号： G06F1/12 ,  H03L7/081 ,  H03L7/08 ,  G06F1/10 ,  H03L7/10 ,  H04B1/16 ,  H03K5/00

摘要： Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

公开(公告)号：US11177816B2

公开(公告)日：2021-11-16

申请号：US16949180

申请日：2020-10-19

申请人： Analog Devices, Inc.

发明人： Neil E. Weeks ,  Reuben P. Nelson

IPC分类号： H03L7/107 ,  H03L7/08 ,  G06F1/12 ,  G06F1/10 ,  H04B1/16 ,  H03K5/00

摘要： Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

公开(公告)号：US20210036706A1

公开(公告)日：2021-02-04

申请号：US16949180

申请日：2020-10-19

申请人： Analog Devices, Inc.

发明人： Neil E. Weeks ,  Reuben P. Nelson

IPC分类号： H03L7/081 ,  H03L7/08 ,  G06F1/12 ,  G06F1/10

摘要： Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

公开(公告)号：US20190004563A1

公开(公告)日：2019-01-03

申请号：US16011970

申请日：2018-06-19

申请人： Analog Devices, Inc.

发明人： Reuben P. Nelson ,  Neil E. Weeks

IPC分类号： G06F1/10 ,  G06F1/12 ,  G06F1/08 ,  H03L7/093 ,  H03L7/16

摘要： Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.