公开(公告)号：US10749535B2

公开(公告)日：2020-08-18

申请号：US16011970

申请日：2018-06-19

申请人： Analog Devices, Inc.

发明人： Reuben P. Nelson ,  Neil E. Weeks

IPC分类号： G06F1/12 ,  H03L7/081 ,  H03L7/08 ,  G06F1/10 ,  H03L7/10 ,  H04B1/16 ,  H03K5/00

摘要： Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

公开(公告)号：US20160277030A1

公开(公告)日：2016-09-22

申请号：US14741984

申请日：2015-06-17

申请人： ANALOG DEVICES, INC.

发明人： Oscar Sebastian Burbano ,  Matthew D. McShea ,  Peter Derounian ,  Reuben P. Nelson ,  Ziwei Zheng ,  Brad P. Jeffries

IPC分类号： H03K23/40 ,  H03L7/06

CPC分类号： H03K23/40 ,  G06F1/022 ,  H03K21/00 ,  H03K21/38 ,  H03K23/00 ,  H03K23/58 ,  H03K23/662 ,  H03K23/665

摘要： An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.

摘要翻译： 公开了一种具有动态相位和脉冲宽度控制的敏捷频率合成器。 一方面，频率合成器包括：计数电路，被配置为通过调整值来修改存储的计数值。 频率合成器还包括输出时钟发生器，其被配置为产生具有上升沿和下降沿的输出时钟信号，所述上升沿和下降沿至少部分地基于满足计数阈值的所存储的计数值。 计数电路还被配置为至少部分地改变计数电路的调整速率来改变输出时钟信号的周期或相位中的至少一个。

公开(公告)号：US11705914B2

公开(公告)日：2023-07-18

申请号：US17454221

申请日：2021-11-09

申请人： Analog Devices, Inc.

发明人： Reuben P. Nelson

IPC分类号： H03L7/08 ,  H03L7/107 ,  G06F1/12 ,  G06F1/10 ,  H04B1/16 ,  H03K5/00

CPC分类号： H03L7/1075 ,  G06F1/10 ,  G06F1/12 ,  H03L7/0807 ,  H03K2005/00143 ,  H03L2207/50 ,  H04B1/16

摘要： Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

公开(公告)号：US20190007052A1

公开(公告)日：2019-01-03

申请号：US16011956

申请日：2018-06-19

申请人： Analog Devices, Inc.

发明人： Reuben P. Nelson

IPC分类号： H03L7/085 ,  H03L7/099

摘要： Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

公开(公告)号：US20230308104A1

公开(公告)日：2023-09-28

申请号：US18326348

申请日：2023-05-31

申请人： Analog Devices, Inc.

发明人： Reuben P. Nelson

IPC分类号： H03L7/107 ,  H03L7/08 ,  G06F1/12 ,  G06F1/10

CPC分类号： H03L7/1075 ,  H03L7/0807 ,  G06F1/12 ,  G06F1/10 ,  H03L2207/50 ,  H04B1/16

摘要： Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

公开(公告)号：US20190007055A1

公开(公告)日：2019-01-03

申请号：US16011963

申请日：2018-06-19

申请人： Analog Devices, Inc.

发明人： Reuben P. Nelson

IPC分类号： H03L7/093 ,  G04F10/00 ,  H03L7/099 ,  H03K5/08 ,  H03K5/133

摘要： Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

公开(公告)号：US20210036706A1

公开(公告)日：2021-02-04

申请号：US16949180

申请日：2020-10-19

申请人： Analog Devices, Inc.

发明人： Neil E. Weeks ,  Reuben P. Nelson

IPC分类号： H03L7/081 ,  H03L7/08 ,  G06F1/12 ,  G06F1/10

摘要： Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

公开(公告)号：US20190004565A1

公开(公告)日：2019-01-03

申请号：US16012017

申请日：2018-06-19

申请人： Analog Devices, Inc.

发明人： Reuben P. Nelson

IPC分类号： G06F1/14 ,  G06F1/12 ,  H03L7/085

摘要： Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

公开(公告)号：US20190004563A1

公开(公告)日：2019-01-03

申请号：US16011970

申请日：2018-06-19

申请人： Analog Devices, Inc.

发明人： Reuben P. Nelson ,  Neil E. Weeks

IPC分类号： G06F1/10 ,  G06F1/12 ,  G06F1/08 ,  H03L7/093 ,  H03L7/16

摘要： Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

公开(公告)号：US08957700B2

公开(公告)日：2015-02-17

申请号：US13631505

申请日：2012-09-28

申请人： Analog Devices, Inc.

发明人： Reuben P. Nelson

IPC分类号： H03K17/16

CPC分类号： H03M11/24 ,  H03K19/0005 ,  H03K19/018585

摘要： Apparatus and method for digital configuration of integrated circuits (ICs) are provided herein. In certain implementations, an IC includes an impedance sensing circuit and at least one pin used for digital configuration. The impedance sensing circuit can detect an impedance value of an external passive network electrically connected to the pin, and can digitally configure the IC based on the detected impedance. For example, an end-user can connect an external resistor of a particular resistance to the pin, and the impedance sensing circuit can sense or detect the external resistor's resistance and digitally configure the IC based on the detected resistance. Accordingly, an end-user can digitally configure the IC by connecting a passive external component corresponding to a desired digital configuration to the pin. In certain implementations, the IC includes multiple pins, and the digital configuration is based on the impedances detected on each of the pins.

摘要翻译： 本文提供了集成电路（IC）的数字配置的装置和方法。 在某些实现中，IC包括阻抗感测电路和用于数字配置的至少一个引脚。 阻抗感测电路可以检测与引脚电连接的外部无源网络的阻抗值，并且可以根据检测到的阻抗对IC进行数字配置。 例如，最终用户可以连接一个特定电阻的外部电阻与引脚，阻抗感测电路可以感测或检测外部电阻的电阻，并根据检测到的电阻对IC进行数字配置。 因此，最终用户可以通过将对应于期望的数字配置的无源外部组件连接到引脚来数字地配置IC。 在某些实现中，IC包括多个引脚，并且数字配置基于在每个引脚上检测到的阻抗。