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公开(公告)号：US11705914B2
公开(公告)日：2023-07-18
申请号：US17454221
申请日：2021-11-09
Applicant: Analog Devices, Inc.
Inventor： Reuben P. Nelson
CPC classification number: H03L7/1075 , G06F1/10 , G06F1/12 , H03L7/0807 , H03K2005/00143 , H03L2207/50 , H04B1/16
Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
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公开(公告)号：US20190007052A1
公开(公告)日：2019-01-03
申请号：US16011956
申请日：2018-06-19
Applicant: Analog Devices, Inc.
Inventor： Reuben P. Nelson
Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
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公开(公告)号：US12212328B2
公开(公告)日：2025-01-28
申请号：US18326348
申请日：2023-05-31
Applicant: Analog Devices, Inc.
Inventor： Reuben P. Nelson
Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
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公开(公告)号：US10749535B2
公开(公告)日：2020-08-18
申请号：US16011970
申请日：2018-06-19
Applicant: Analog Devices, Inc.
Inventor： Reuben P. Nelson , Neil E. Weeks
Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
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公开(公告)号：US20160277030A1
公开(公告)日：2016-09-22
申请号：US14741984
申请日：2015-06-17
Applicant: ANALOG DEVICES, INC.
Inventor： Oscar Sebastian Burbano , Matthew D. McShea , Peter Derounian , Reuben P. Nelson , Ziwei Zheng , Brad P. Jeffries
CPC classification number: H03K23/40 , G06F1/022 , H03K21/00 , H03K21/38 , H03K23/00 , H03K23/58 , H03K23/662 , H03K23/665
Abstract: An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.
Abstract translation: 公开了一种具有动态相位和脉冲宽度控制的敏捷频率合成器。 一方面，频率合成器包括：计数电路，被配置为通过调整值来修改存储的计数值。 频率合成器还包括输出时钟发生器，其被配置为产生具有上升沿和下降沿的输出时钟信号，所述上升沿和下降沿至少部分地基于满足计数阈值的所存储的计数值。 计数电路还被配置为至少部分地改变计数电路的调整速率来改变输出时钟信号的周期或相位中的至少一个。
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Patent Agency Ranking
公开(公告)号：US20230308104A1
公开(公告)日：2023-09-28
申请号：US18326348
申请日：2023-05-31
Applicant: Analog Devices, Inc.
Inventor： Reuben P. Nelson
CPC classification number: H03L7/1075 , H03L7/0807 , G06F1/12 , G06F1/10 , H03L2207/50 , H04B1/16
Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
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公开(公告)号：US20190007055A1
公开(公告)日：2019-01-03
申请号：US16011963
申请日：2018-06-19
Applicant: Analog Devices, Inc.
Inventor： Reuben P. Nelson
Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
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公开(公告)号：US20210036706A1
公开(公告)日：2021-02-04
申请号：US16949180
申请日：2020-10-19
Applicant: Analog Devices, Inc.
Inventor： Neil E. Weeks , Reuben P. Nelson
Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
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公开(公告)号：US20190004565A1
公开(公告)日：2019-01-03
申请号：US16012017
申请日：2018-06-19
Applicant: Analog Devices, Inc.
Inventor： Reuben P. Nelson
Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
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公开(公告)号：US20190004563A1
公开(公告)日：2019-01-03
申请号：US16011970
申请日：2018-06-19
Applicant: Analog Devices, Inc.
Inventor： Reuben P. Nelson , Neil E. Weeks
Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
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