Logarithmic current to voltage converters

    公开(公告)号:US12271216B2

    公开(公告)日:2025-04-08

    申请号:US18040025

    申请日:2021-11-30

    Inventor: Petrus M. Stroet

    Abstract: Apparatus and methods for logarithmic current to voltage conversion are disclosed herein. In certain embodiments, a logarithmic current to voltage converter includes an input terminal that receives an input current, an output terminal that provides a logarithmic output voltage, a first field-effect transistor (FET) having a gate connected to the input terminal, a first bipolar transistor having a collector connected to the input terminal and an emitter connected to the output terminal, and a stacked transistor connected to the output terminal and to the first FET to form a feedback loop. For example, the stacked transistor can correspond to a second bipolar transistor having a collector connected to the output terminal and a base connected to the source of the first FET, or to a second FET having a drain connected to the output terminal and a gate connected to the source of the first FET.

    APPARATUS AND METHODS FOR INPUT RECOVERY OF LOGARITHMIC TRANSIMPEDANCE AMPLIFIERS

    公开(公告)号:US20250070727A1

    公开(公告)日:2025-02-27

    申请号:US18795856

    申请日:2024-08-06

    Inventor: Petrus M. Stroet

    Abstract: Apparatus and methods for preventing overshoot for a high-to-low input current transient of a logarithmic transimpedance amplifier are disclosed. In certain embodiments, an amplifier system includes a logarithmic transimpedance amplifier having an input that receives an input current signal, and a current pulse injection circuit that injects a current pulse into the input of the logarithmic transimpedance amplifier in response to detecting a transition of the input current signal from a high current value to a low current value.

    LOGARITHMIC CURRENT TO VOLTAGE CONVERTERS
    4.
    发明公开

    公开(公告)号:US20230409066A1

    公开(公告)日:2023-12-21

    申请号:US18040025

    申请日:2021-11-30

    Inventor: Petrus M. Stroet

    CPC classification number: G05F1/59 G05F1/468 H01L31/02019

    Abstract: Apparatus and methods for logarithmic current to voltage conversion are disclosed herein. In certain embodiments, a logarithmic current to voltage converter includes an input terminal that receives an input current, an output terminal that provides a logarithmic output voltage, a first field-effect transistor (FET) having a gate connected to the input terminal, a first bipolar transistor having a collector connected to the input terminal and an emitter connected to the output terminal, and a stacked transistor connected to the output terminal and to the first FET to form a feedback loop. For example, the stacked transistor can correspond to a second bipolar transistor having a collector connected to the output terminal and a base connected to the source of the first FET, or to a second FET having a drain connected to the output terminal and a gate connected to the source of the first FET.

    LOGARITHMIC CURRENT TO VOLTAGE CONVERTERS WITH EMITTER RESISTANCE COMPENSATION

    公开(公告)号:US20240250647A1

    公开(公告)日:2024-07-25

    申请号:US18410182

    申请日:2024-01-11

    Inventor: Petrus M. Stroet

    CPC classification number: H03F3/3432 H03F1/302 H03F3/45085 H03F3/456

    Abstract: Logarithmic current-to-voltage converters with emitter resistance compensation are disclosed herein. In certain embodiments, a logarithmic current-to-voltage converter includes a logarithmic bipolar transistor that converts an input current to a logarithmic voltage, and an emitter resistance compensation circuit that includes a replica of the logarithmic bipolar transistor. The emitter resistance compensation circuit processes a copy of the input current to generate an emitter resistance compensation signal that adjusts the logarithmic voltage to correct for an error introduced by an emitter resistance of the logarithmic bipolar transistor. By providing emitter resistance compensation in this matter, logarithmic current-to-voltage conversion with high accuracy and low log error is achieved.

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