Differential charge reduction
    1.
    发明授权
    Differential charge reduction 有权
    差分电荷减少

    公开(公告)号:US08941439B2

    公开(公告)日:2015-01-27

    申请号:US13769096

    申请日:2013-02-15

    Abstract: One embodiment relates to an apparatus configured to cancel charge injected on a node of a differential pair of nodes. A dummy circuit element can inject charge on an inverted node to cancel charge injected on a non-inverted node by a switch when the switch is switched off. In addition, another dummy circuit element can inject charge on the non-inverted node to cancel charge injected on the inverted node by another switch when the other switch is switched off. These dummy circuits elements can be cross-coupled.

    Abstract translation: 一个实施例涉及一种被配置为消除注入在差分对节点上的节点上的电荷的装置。 假电路元件可以在反相节点上注入电荷,以在开关断开时通过开关取消在非反相节点上注入的电荷。 此外,另一个虚拟电路元件可以在非反相节点上注入电荷,以在另一个开关断开时通过另一个开关来取消在反相节点上注入的电荷。 这些虚拟电路元件可以是交叉耦合的。

    Boosted switch drivers for high-speed signal switching

    公开(公告)号:US11121713B1

    公开(公告)日:2021-09-14

    申请号:US17007126

    申请日:2020-08-31

    Abstract: An example boosted switch driver circuit includes two branches. The first branch includes a first transistor. The second branch includes a second transistor and a level shifter circuit. One of the transistors is an N-type transistor and the other one is a P-type transistor. The circuit is configured to split an input clock signal between the first branch and the second branch, so that a portion of the input clock signal split to the first branch is provided to the first transistor, and a portion of the input clock signal split to the second branch is level-shifted by the level shifter circuit to generate a level-shifted input clock signal and the level-shifted input clock signal is provided to the second transistor. The circuit is further configured to combine an output of the first transistor and an output of the second transistor to generate an output clock signal.

    Passive switched capacitor circuit for sampling and amplification

    公开(公告)号:US10062450B1

    公开(公告)日:2018-08-28

    申请号:US15629057

    申请日:2017-06-21

    Abstract: In pipelined analog-to-digital converters (ADCs), a passive switched capacitor (PSWC) circuit can be used in a multiplying analog-to-digital converter (MDAC), which generates an analog output being fed to a subsequent stage. Complementary analog input signals are sampled respectively onto first and second capacitors, which are stacked to provide gain. The first capacitor is positioned between a first input switch and an output node of the PSWC circuit, and the second capacitor is positioned between the second input switch and a digital-to-analog converter (DAC) output. The topology advantageously isolates common modes of the complementary analog input signals, the DAC output, and the output of the PSWC circuit. As a result, the topology offers more degrees of freedom in the overall circuit design when stages having the MDAC are cascaded, resulting in pipelined ADCs with a more elegant design with lower noise and lower power consumption.

    DIFFERENTIAL CHARGE REDUCTION
    4.
    发明申请
    DIFFERENTIAL CHARGE REDUCTION 有权
    差异充电减少

    公开(公告)号:US20140232460A1

    公开(公告)日:2014-08-21

    申请号:US13769096

    申请日:2013-02-15

    Abstract: One embodiment relates to an apparatus configured to cancel charge injected on a node of a differential pair of nodes. A dummy circuit element can inject charge on an inverted node to cancel charge injected on a non-inverted node by a switch when the switch is switched off. In addition, another dummy circuit element can inject charge on the non-inverted node to cancel charge injected on the inverted node by another switch when the other switch is switched off. These dummy circuits elements can be cross-coupled.

    Abstract translation: 一个实施例涉及一种被配置为消除注入在差分对节点上的节点上的电荷的装置。 假电路元件可以在反相节点上注入电荷,以在开关断开时通过开关取消在非反相节点上注入的电荷。 此外,另一个虚拟电路元件可以在非反相节点上注入电荷,以在另一个开关断开时通过另一个开关来取消在反相节点上注入的电荷。 这些虚拟电路元件可以是交叉耦合的。

Patent Agency Ranking