公开(公告)号：US5384279A

公开(公告)日：1995-01-24

申请号：US144091

申请日：1993-10-27

申请人： Andre Stolmeijer ,  Paulus M. T. M. Van Attekum ,  Hubertus Den Blanken ,  Paulus A. Van Der Plas ,  Reinier De Werdt

发明人： Andre Stolmeijer ,  Paulus M. T. M. Van Attekum ,  Hubertus Den Blanken ,  Paulus A. Van Der Plas ,  Reinier De Werdt

IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/70

CPC分类号： H01L21/823807 ,  H01L21/2652 ,  H01L27/0928 ,  Y10S438/919

摘要： A method of manufacturing a semiconductor device is set forth, comprising a silicon body (1) having a surface (4) where there are situated a number of semiconductor regions (5, 6) and field oxide regions (7). The semiconductor regions is formed, after the field oxide regions have been provided, by implantations of n-type and p-type dopants. In accordance with the invention the implantations with the n-type dopant (10, 11, 14), which are performed using an implantation mask (8) provided on the surface and comprising openings (9) at the area of a part of the semiconductor regions (5) to be formed, are combined with the implantations with the p-type dopant (12, 13, 15) which are carried out without using the implantation mask. Thus, the semiconductor regions (5, 6) are realised by means of a single implantation mask (8).

摘要翻译： 提出了一种制造半导体器件的方法，包括具有表面（4）的硅体（1），其中位于多个半导体区域（5,6）和场氧化物区域（7）的表面（4）。 在提供场氧化物区域之后，通过n型和p型掺杂剂的注入形成半导体区域。 根据本发明，使用设置在表面上的注入掩模（8）进行n型掺杂剂（10,11,14）的注入，并且在半导体的一部分区域包括开口（9） 要形成的区域（5）与不使用注入掩模执行的p型掺杂剂（12,13,15）的注入组合。 因此，通过单个注入掩模（8）实现半导体区域（5,6）。

公开(公告)号：US5015602A

公开(公告)日：1991-05-14

申请号：US522490

申请日：1990-05-10

申请人： Paulus A. Van Der Plas ,  Reinier De Werdt

发明人： Paulus A. Van Der Plas ,  Reinier De Werdt

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/762

CPC分类号： H01L21/76229

摘要： A method of manufacturing a semiconductor device, in which a depression (1,2,3) in a surface (4) of a semiconductor substrate (5) is filled by covering it with a preplanarized filling layer (8,19,22) and a further planarization layer (9), after which the substrate (5) is brought into contact with an etchant, in which both layers (8,19,22) and (9) are etched at substantially the same rate. According to the invention, the preplanarized filling layer (8,19,22) is formed by covering the surface (4) with a layer of filling material (6) and then removing it beside the depression (1,2,3) over part of its thickness. Thus, the depression (1,2,3) is filled homogeneously in a comparatively simple manner with material of the filling layer (6).

摘要翻译： 一种制造半导体器件的方法，其中半导体衬底（5）的表面（4）中的凹陷（1,2,3）通过用预共面填充层（8,19,22）覆盖而被填充，并且 另外的平坦化层（9），然后使衬底（5）与蚀刻剂接触，其中两个层（8,19,22）和（9）以基本上相同的速率被蚀刻。 根据本发明，通过用一层填充材料（6）覆盖表面（4），然后在凹部（1,2,3）上方部分地将其去除，形成预平面化填充层（8,19,22） 的厚度。 因此，用填充层（6）的材料以相对简单的方式均匀地填充凹陷（1,2,3）。

公开(公告)号：US5248892A

公开(公告)日：1993-09-28

申请号：US693765

申请日：1991-04-26

申请人： Leonardus J. Van Roozendaal ,  Reinier De Werdt

发明人： Leonardus J. Van Roozendaal ,  Reinier De Werdt

IPC分类号： H01L27/02

CPC分类号： H01L27/0251 ,  H01L27/0255

摘要： The invention relates to an integrated circuit connected via a first connection conductor (61) to a first contact area. Between the first connection conductor (61) and a second connection conductor (63), a protection element (8) is connected, which protects the circuit especially from electrostatic discharges. The protection element (8) comprises an active zone (81), which is covered with metal silicide (15) and forms a pn junction (86) with the adjoining part (83) of the semiconductor body (10). On the metal silicide (15), the active zone (81) is provided with an electrode (16), through which the zone (81) is connected to the first connection conductor (61). The use of metal silicide in the integrated circuit in itself has great advantages, but in the protection element the metal silicide layer is found to give rise to a considerably lower reliability. The invention has for its object to obviate this disadvantage without it being necessary to modify the manufacturing process. According to the invention, in order to improve the uniformity of the current distribution over the pn junction (86), between the electrode (16) and the pn junction (86), a resistance element (9, 91, 92) is connected in series with the protection element (8) directly to the active zone (81) of the protection element (8), whose width is substantially equal to the width of the active zone (81). Such a resistance element can be entirely realized within the process of manufacturing the integrated circuit.

摘要翻译： 本发明涉及通过第一连接导体（61）连接到第一接触区域的集成电路。 在第一连接导体（61）和第二连接导体（63）之间连接保护元件（8），保护电路特别是静电放电。 保护元件（8）包括被金属硅化物（15）覆盖并与半导体本体（10）的邻接部分（83）形成pn结（86）的有源区（81）。 在金属硅化物（15）上，有源区（81）设置有电极（16），区域（81）通过该电极连接到第一连接导体（61）。 在集成电路中使用金属硅化物本身具有很大的优点，但是在保护元件中，发现金属硅化物层产生相当低的可靠性。 本发明的目的是消除这种缺点，而不需要修改制造过程。 根据本发明，为了提高pn结（86），电极（16）和pn结（86）之间的电流分布的均匀性，电阻元件（9,91,92）连接在 与保护元件（8）直接连接到保护元件（8）的有源区（81），其宽度基本上等于有源区（81）的宽度。 这样的电阻元件可以在制造集成电路的过程中完全实现。