公开(公告)号：US5384279A

公开(公告)日：1995-01-24

申请号：US144091

申请日：1993-10-27

申请人： Andre Stolmeijer ,  Paulus M. T. M. Van Attekum ,  Hubertus Den Blanken ,  Paulus A. Van Der Plas ,  Reinier De Werdt

发明人： Andre Stolmeijer ,  Paulus M. T. M. Van Attekum ,  Hubertus Den Blanken ,  Paulus A. Van Der Plas ,  Reinier De Werdt

IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/70

CPC分类号： H01L21/823807 ,  H01L21/2652 ,  H01L27/0928 ,  Y10S438/919

摘要： A method of manufacturing a semiconductor device is set forth, comprising a silicon body (1) having a surface (4) where there are situated a number of semiconductor regions (5, 6) and field oxide regions (7). The semiconductor regions is formed, after the field oxide regions have been provided, by implantations of n-type and p-type dopants. In accordance with the invention the implantations with the n-type dopant (10, 11, 14), which are performed using an implantation mask (8) provided on the surface and comprising openings (9) at the area of a part of the semiconductor regions (5) to be formed, are combined with the implantations with the p-type dopant (12, 13, 15) which are carried out without using the implantation mask. Thus, the semiconductor regions (5, 6) are realised by means of a single implantation mask (8).

摘要翻译： 提出了一种制造半导体器件的方法，包括具有表面（4）的硅体（1），其中位于多个半导体区域（5,6）和场氧化物区域（7）的表面（4）。 在提供场氧化物区域之后，通过n型和p型掺杂剂的注入形成半导体区域。 根据本发明，使用设置在表面上的注入掩模（8）进行n型掺杂剂（10,11,14）的注入，并且在半导体的一部分区域包括开口（9） 要形成的区域（5）与不使用注入掩模执行的p型掺杂剂（12,13,15）的注入组合。 因此，通过单个注入掩模（8）实现半导体区域（5,6）。

公开(公告)号：US06232221B1

公开(公告)日：2001-05-15

申请号：US09260001

申请日：1999-03-02

申请人： Khanh Tran ,  Sunil Mehta ,  Andre Stolmeijer

发明人： Khanh Tran ,  Sunil Mehta ,  Andre Stolmeijer

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Borderless vias are formed by depositing a hard dielectric mask layer on the upper surface of a lower metal feature and forming sidewall spacers on the side surfaces of the metal feature and mask layer. A dielectric interlayer is deposited and a misaligned through-hole formed therein by etching. The dielectric material of the sidewall spacer and dielectric material of the dielectric interlayer are different. The etchant employed to form the through-hole exhibits a high selectivity with respect to the sidewall spacer material. The dielectric mask layer enables the formation of a sidewall spacer extending above the metal feature such that, after etching to form the misaligned through-hole, the sidewall spacer covers the side surface of the metal feature.

摘要翻译： 通过在下金属特征的上表面上沉积硬介电掩模层并在金属特征和掩模层的侧表面上形成侧壁间隔而形成无边界通孔。 沉积电介质中间层，通过蚀刻形成不对准的通孔。 电介质中间层的侧壁间隔物和电介质材料的电介质材料是不同的。 用于形成通孔的蚀刻剂相对于侧壁间隔物材料显示出高选择性。 电介质掩模层能够形成在金属特征之上延伸的侧壁间隔，使得在蚀刻以形成未对准的通孔之后，侧壁间隔物覆盖金属特征的侧表面。

公开(公告)号：US5955751A

公开(公告)日：1999-09-21

申请号：US133999

申请日：1998-08-13

申请人： Mehul D. Shroff ,  Rajiv Jain ,  Andre Stolmeijer ,  Kathryn E. Gordon

发明人： Mehul D. Shroff ,  Rajiv Jain ,  Andre Stolmeijer ,  Kathryn E. Gordon

IPC分类号： H01L23/525 ,  H01L23/52 ,  H01L23/528

CPC分类号： H01L23/5252 ,  H01L23/525 ,  H01L2924/0002

摘要： A field programmable gate array has antifuses disposed over logic modules. Each of these antifuses includes a conductive plug and an overlaying region of programmable material (for example, amorphous silicon). To program one of these antifuses, an electric connection is formed through the programmable material to couple the conductive plug to a metal conductor that overlays the region of programmable material. The metal conductor includes a layer of a barrier metal to separate another metal of the conductor (for example, aluminum from an aluminum layer) from migrating into the programmable material when the antifuse is unprogrammed. In some embodiments, less than three percent of all antifuses of the field programmable gate array has a corner (from the top-down perspective) of the region of programmable material that is disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse. In some embodiments, less than seventy-five percent of all antifuses of the field programmable gate array have an edge of the region of programmable material disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse. Other antifuse structures and methods are also disclosed for preventing programmable material corners and/or edges from compromising yield and/or reliability of programmable devices.

公开(公告)号：US5654915A

公开(公告)日：1997-08-05

申请号：US663603

申请日：1996-06-14

申请人： Andre Stolmeijer ,  Christopher Petti

发明人： Andre Stolmeijer ,  Christopher Petti

IPC分类号： G11C8/14 ,  G11C11/412 ,  G11C11/419

CPC分类号： G11C11/412 ,  G11C8/14

摘要： The present invention relates to a solid-state bi-stable circuit functioning as a six-bulk transistor static memory cell, the circuit comprising a plurality of bitlines and at least a first and second reference line, all of which are positioned in parallel with a plurality of wordlines. The circuit further comprises a plurality of transistors including a first and second load transistor, a first and a second pull-down transistor and a first and a second access transistor, in which each of the plurality of transistors includes a gate, source and drain. The gates of the plurality of transistors are positioned in parallel to minimize area usage.

摘要翻译： 本发明涉及用作六体晶体管静态存储单元的固态双稳电路，该电路包括多个位线和至少第一和第二参考线，所有这些都与 多个字线。 该电路还包括多个晶体管，其包括第一和第二负载晶体管，第一和第二下拉晶体管以及第一和第二存取晶体管，其中多个晶体管中的每一个包括栅极，源极和漏极。 多个晶体管的栅极并联放置以最小化区域使用。

公开(公告)号：US06107165A

公开(公告)日：2000-08-22

申请号：US133998

申请日：1998-08-13

申请人： Rajiv Jain ,  Andre Stolmeijer ,  Mehul D. Shroff

发明人： Rajiv Jain ,  Andre Stolmeijer ,  Mehul D. Shroff

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： A metal-to-metal conductive plug-type antifuise has a conductive plug disposed in an opening in an insulating layer. A programmable material feature (for example, amorphous silicon) overlies the conductive plug. A conductor involving a metal (for example, aluminum or copper) that migrates in the programmable material overlies the programmable material. To prevent migration of metal from the conductor into the programmable material when the antifuse is not programmed, the conductor has a layer of barrier metal between the metal that migrates and the programmable material. In some embodiments, there are two layers of barrier metal. An airbreak after formation of the first barrier metal layer improves the ability of the barrier metal to prevent diffusion between the programmable material and the overlying conductor. The airbreak may stuff grain boundaries in the upper surface of the first barrier metal and/or may cause the first barrier metal layer to have different grains and/or a different grain orientation than the overlaying second barrier metal layer. In some embodiments, a capping layer over the top surface of the programmable material protects the underlying programmable material during an ashing step when a mask used to etch the programmable material is removed. The capping layer and the programmable material form a capping layer/programmable material layer stack within the antifuse underneath the two barrier metal layers. The capping layer may also be made of a barrier metal and constitute an additional barrier.

摘要翻译： 金属对金属导电插塞型防腐剂具有设置在绝缘层的开口中的导电插塞。 可编程材料特征（例如，非晶硅）覆盖在导电插塞上。 涉及在可编程材料中迁移的金属（例如铝或铜）的导体覆盖在可编程材料上。 为了防止当反熔丝未编程时金属从导体迁移到可编程材料中，导体在迁移的金属和可编程材料之间具有一层阻挡金属。 在一些实施例中，存在两层屏障金属。 在形成第一阻挡金属层之后的空气破裂提高了阻挡金属防止可编程材料与上覆导体之间的扩散的能力。 所述防风剂可以在第一阻挡金属的上表面填充晶界，和/或可使第一阻挡金属层与覆盖的第二阻挡金属层具有不同的晶粒和/或不同的晶粒取向。 在一些实施例中，当可去除用于蚀刻可编程材料的掩模时，可编程材料顶表面上的覆盖层在灰化步骤期间保护底层可编程材料。 封盖层和可编程材料在两个阻挡金属层下面的反熔丝内形成覆盖层/可编程材料层堆叠。 封盖层也可以由阻挡金属制成并构成另外的屏障。

公开(公告)号：US5877066A

公开(公告)日：1999-03-02

申请号：US964431

申请日：1997-11-04

申请人： Andre Stolmeijer ,  Farrokh Omid-Zohoor

发明人： Andre Stolmeijer ,  Farrokh Omid-Zohoor

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： An integrated circuit device has a plurality of active devices which are formed on a semiconductor body. A plurality of narrow isolating regions of insulating material are vertically formed on the semiconductor body such that at least one of the narrow isolating regions separates and thereby isolates adjacent active devices. Essentially all of said isolating regions are substantially equal in width, preferably less than or equal to about 0.5 .mu.m.

摘要翻译： 集成电路器件具有形成在半导体本体上的多个有源器件。 绝缘材料的多个窄隔离区域垂直地形成在半导体本体上，使得至少一个窄隔离区域分离，从而隔离相邻的有源器件。 基本上所有的所述隔离区域的宽度基本相等，优选小于或等于约0.5μm。

公开(公告)号：US5874317A

公开(公告)日：1999-02-23

申请号：US662224

申请日：1996-06-12

申请人： Andre Stolmeijer

发明人： Andre Stolmeijer

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232 ,  Y10S148/05 ,  Y10S148/061

摘要： A method of fabricating an integrated circuit with trenches, without parasitic edge transistors, for isolating FET transistors from each other without degrading the FETs operating characteristics by junction leakage, breakdown or shorting, when a metal silicide is used in the source/drain regions. A silicon wafer is formed with sidewalls on the sides of each area in which a groove is to be etched. In etching the silicon, the sidewalls define the lateral dimension of the trenches. After the trenches are etched, the sidewalls are removed and the trenched are filled with an insulating material using a high density plasma reactor, such as an electron cyclotron resonance (ECR) plasma reactor. This type of reactor simultaneously deposits and sputter etches so that silicon edges at the base of the now removed sidewalls become tapered at an angle of about 45.degree. during deposition. Thus, the profiles of the filled trenches all have tapered tops which reduces the possibility of parasitic edge transistors and any leakage or shorting.

摘要翻译： 一种制造具有沟槽的集成电路的方法，没有寄生边缘晶体管，用于在源极/漏极区域中使用金属硅化物时，将FET晶体管彼此隔离，而不会使FET的工作特性受到结漏电，击穿或短路的影响。 硅晶片在其中要蚀刻凹槽的每个区域的侧面上形成有侧壁。 在蚀刻硅时，侧壁限定沟槽的横向尺寸。 在蚀刻沟槽之后，使用诸如电子回旋共振（ECR）等离子体反应器的高密度等离子体反应器，去除侧壁并且用绝缘材料填充沟槽。 这种类型的反应器同时沉积和溅射蚀刻，使得现在除去的侧壁的底部的硅边缘在沉积期间以约45°的角度变细。 因此，填充沟槽的轮廓都具有锥形顶部，这降低了寄生边缘晶体管的可能性以及任何泄漏或短路。

公开(公告)号：US5834159A

公开(公告)日：1998-11-10

申请号：US635988

申请日：1996-04-22

申请人： Andre Stolmeijer

发明人： Andre Stolmeijer

IPC分类号： H01L21/768 ,  H01L21/027 ,  H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  G03F7/00

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/31144

摘要： The present invention provides a method for fabricating small structures to be employed in integrated circuits formed on a semiconductor substrate. Examples of such small structures include contacts, vias, and metal lines. The method of the present invention employs an image reversal technique to obtain improved feature definition. In forming a feature in a layer of material, a clear field reticle is used to form patterned segments of photoresist each having a size, a shape, and a location substantially identical to the size, the shape, and the location of one of the features intended to be formed in the layer of material. This method is employed instead of using a dark field reticle which forms windows in a photoresist each having a size, a shape, and a location substantially identical to the size, the shape, and the location of one of the features intended to be formed in the layer of material. For small structures, the openings or windows in a photoresist are harder to form than the patterned segments of photoresist. With the method of the present invention which employs a clear field reticle to form a mask comprising patterned segments of photoresist, the limitations of patterning small windows in a photoresist with the use of a dark field reticle are avoided. The accuracy of forming the small structures is thus improved.

摘要翻译： 本发明提供一种用于制造半导体衬底上形成的集成电路中使用的小型结构的方法。 这种小结构的实例包括接触，通孔和金属线。 本发明的方法采用图像反转技术来获得改进的特征定义。 在形成材料层中的特征时，使用清晰的场地掩模版来形成具有尺寸，形状和基本上等于特征之一的尺寸，形状和位置的光刻胶的图案化部分 意图形成在材料层中。 采用这种方法来代替使用在光刻胶中形成窗口的暗场掩模版，每个光刻胶具有尺寸，形状和位置，其大小，形状和预期要形成的特征之一的位置基本相同 材料层。 对于小结构，光致抗蚀剂中的开口或窗口比图案化的光致抗蚀剂段难以形成。 利用本发明的采用清晰的场地掩模版形成包括光刻胶图案的掩模的掩模的方法，避免了使用暗场掩模版对光致抗蚀剂中的小窗口进行图形化的限制。 从而提高了形成小结构的精度。

公开(公告)号：US06627969B1

公开(公告)日：2003-09-30

申请号：US09563091

申请日：2000-05-01

申请人： Rajiv Jain ,  Andre Stolmeijer ,  Mehul D. Shroff

发明人： Rajiv Jain ,  Andre Stolmeijer ,  Mehul D. Shroff

IPC分类号： H01L2900

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-to-metal conductive plug-type antifuse has a conductive plug disposed in an opening in an insulating layer. A programmable material feature (for example, amorphous silicon) overlies the conductive plug. A conductor involving a metal (for example, aluminum or copper) that migrates in the programmable material overlies the programmable material. To prevent migration of metal from the conductor into the programmable material when the antifuse is not programmed, the conductor has a layer of barrier metal between the metal that migrates and the programmable material. In some embodiments, there are two layers of barrier metal. An airbreak after formation of the first barrier metal layer improves the ability of the barrier metal to prevent diffusion between the programmable material and the overlying conductor. The airbreak may stuff grain boundaries in the upper surface of the first barrier metal and/or may cause the first barrier metal layer to have different grains and/or a different grain orientation than the overlaying second barrier metal layer. In some embodiments, a capping layer over the top surface of the programmable material protects the underlying programmable material during an ashing step when a mask used to etch the programmable material is removed. The capping layer and the programmable material form a capping layer/programmable material layer stack within the antifuse underneath the two barrier metal layers. The capping layer may also be made of a barrier metal and constitute an additional barrier.

摘要翻译： 金属对金属导电塞型反熔丝具有设置在绝缘层的开口中的导电插塞。 可编程材料特征（例如，非晶硅）覆盖在导电插塞上。 涉及在可编程材料中迁移的金属（例如铝或铜）的导体覆盖在可编程材料上。 为了防止当反熔丝未编程时金属从导体迁移到可编程材料中，导体在迁移的金属和可编程材料之间具有一层阻挡金属。 在一些实施例中，存在两层屏障金属。 在形成第一阻挡金属层之后的空气破裂提高了阻挡金属防止可编程材料与上覆导体之间的扩散的能力。 所述防风剂可以在第一阻挡金属的上表面填充晶界，和/或可使第一阻挡金属层与覆盖的第二阻挡金属层具有不同的晶粒和/或不同的晶粒取向。 在一些实施例中，当可去除用于蚀刻可编程材料的掩模时，可编程材料顶表面上的覆盖层在灰化步骤期间保护底层可编程材料。 封盖层和可编程材料在两个阻挡金属层下面的反熔丝内形成覆盖层/可编程材料层堆叠。 封盖层也可以由阻挡金属制成并构成另外的屏障。

公开(公告)号：US5834845A

公开(公告)日：1998-11-10

申请号：US532915

申请日：1995-09-21

申请人： Andre Stolmeijer

发明人： Andre Stolmeijer

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/52

CPC分类号： H01L23/5226 ,  H01L21/768 ,  H01L21/76807 ,  H01L23/5283 ,  H01L2924/0002

摘要： A novel interconnect layout method and metallization scheme is provided that simplifies the process of fabricating multilayer interconnects. The process of the present invention provides a multilevel interconnect structure formed solely from patterned metal layers stacked on top of each other. Both interconnect lines which form electrical connections along horizontal paths, as well as contacts which form electrical connections along vertical paths, can be formed using patterned metal interconnects as building-blocks. No specific process module is needed for contact layers. The use of patterned metal layers formed from the same process modules makes both design and construction of multilayer interconnects simpler. Accordingly, the manufacturing process is simplified, thus resulting in lower cost. To form thicker metal layers for the purpose of constructing thick interconnect lines, two or more patterned metal layers may be stacked on each other. In this manner, vertical low ohmic bussing is made possible.

摘要翻译： 提供了一种新颖的互连布局方法和金属化方案，其简化了制造多层互连的过程。 本发明的方法提供了仅由堆叠在彼此顶部的图案化金属层形成的多层互连结构。 可以使用图案化金属互连作为构建块来形成沿水平路径形成电连接的两条互连线以及沿垂直路径形成电连接的触点。 接触层不需要特定的过程模块。 使用由相同工艺模块形成的图案化金属层使得多层互连的设计和构造更简单。 因此，制造过程简化，从而导致成本降低。 为了形成较厚的金属层，为了构造厚的互连线，两个或多个图案化的金属层可以彼此堆叠。 以这种方式，垂直低欧姆总线成为可能。