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公开(公告)号：US07013256B2
公开(公告)日：2006-03-14
申请号：US10021269
申请日：2001-12-12
CPC分类号： G06F11/3632 , G06F9/30072 , G06F11/3648
摘要： A computer system for executing instructions having assigned guard indicators, comprises instruction supply circuitry, pipelined execution units for receiving instructions from the supply circuitry together with at least one guard indicator selected from a set of guard indicators, the execution unit including a master guard value store containing master values for the guard indicators, and circuitry for resolving the guard values in the execution pipeline and providing a signal to indicate whether the pipeline is committed to the execution of the instruction, and an emulator having watch circuitry for effecting a watch on selected instructions supplied to the execution pipeline and synchronising circuitry for correlating resolution of the guard indicator of each selected instruction with a program count for that instruction.
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2.发明申请Computer system with debug facility for debugging a processor capable of predicated execution 有权具有调试功能的计算机系统，用于调试能够进行预定执行的处理器公开(公告)号：US20060184775A1
公开(公告)日：2006-08-17
申请号：US11384024
申请日：2006-03-17
IPC分类号： G06F9/44
CPC分类号： G06F11/3656 , G06F9/3842
摘要： A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.
摘要翻译： 描述了一种具有增强型集成调试功能的计算机系统。 根据一个方面，执行指令序列的逐步执行，其中每个指令被保护。 如果在保护解决之后，执行指令，则执行转移程序。 如果指令未提交，则执行该顺序中的下一条指令。 根据另一方面，可以通过读取与调试指令相关联的失速属性，或响应来自片上仿真单元的失速命令，在解码单元处设置失速状态。
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3.发明授权Computer system with a debug facility for a pipelined processor using predicated execution 有权具有使用预定执行的流水线处理器调试功能的计算机系统公开(公告)号：US07441109B2
公开(公告)日：2008-10-21
申请号：US11384024
申请日：2006-03-17
IPC分类号： G06F7/38
CPC分类号： G06F11/3656 , G06F9/3842
摘要： A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.
摘要翻译： 描述了一种具有增强型集成调试功能的计算机系统。 根据一个方面，执行指令序列的逐步执行，其中每个指令被保护。 如果在保护解决之后，执行指令，则执行转移程序。 如果指令未提交，则执行该顺序中的下一条指令。 根据另一方面，可以通过读取与调试指令相关联的失速属性，或响应来自片上仿真单元的失速命令，在解码单元处设置失速状态。
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4.发明授权Computer system with two debug watch modes for controlling execution of guarded instructions upon breakpoint detection 有权具有两个调试监视模式的计算机系统，用于在断点检测时控制执行保护指令公开(公告)号：US07240185B2
公开(公告)日：2007-07-03
申请号：US09748785
申请日：2000-12-22
IPC分类号： G06F11/36
CPC分类号： G06F11/3656
摘要： A computer system is provided with precise and non-precise watch modes. The computer system is a pipelined system in which the fate of an instruction is determined at the decode stage. Once instructions have been decoded, it is not possible for them to be “killed” later in the pipeline. According to the precise watch mode, instructions are held at the decode stage until the guard value has been resolved to determine whether or not that instruction is committed. Actions of the decode unit are determined in dependence on whether or not the instruction is committed when the guard has been resolved. According to a non-precise watch mode, instructions continue to be decoded and executed normally until a breakpoint instruction has had its guard resolved. At that point, an on-chip emulator can take over operations of the processor in a divert mode. The computer system can take into account different intrusion levels while implementing the watch modes.
摘要翻译： 计算机系统提供精确和非精确的手表模式。 计算机系统是在解码阶段确定指令的命运的流水线系统。 一旦指令被解码，它们不可能在后期被“杀死”。 根据精确的观察模式，在解码阶段保持指令，直到保护值被解析以确定该指令是否被提交。 解码单元的动作取决于当防护件已被解决时是否提交指令。 根据不精确的观察模式，指令继续被解码并正常执行，直到断点指令得到保护解决为止。 在这一点上，片上仿真器可以在转接模式下接管处理器的操作。 计算机系统可以在实现手表模式时考虑到不同的入侵级别。
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公开(公告)号：US06832334B2
公开(公告)日：2004-12-14
申请号：US09748763
申请日：2000-12-22
IPC分类号： H02H305
CPC分类号： G06F11/3636 , G06F11/3648
摘要： A computer system includes instruction fetch circuitry, decode circuitry to decode instructions and identify any registers to be used and dispatch circuitry to dispatch instructions to one or more execution units, said system including emulator circuitry for debug operations which is arranged to watch data values in one or more selected registers modified during execution of the instructions, the computer circuitry further comprising a register watch store for identifying one or more registers to be watched, comparator circuitry for comparing registers identified by said decode circuitry with registers identified in said register watch store and providing a hit signal for hits in the comparison, and instruction insertion circuitry responsive to hit signals to insert in the instruction sequence to an execution unit a store instruction to store in a location accessible by the emulation circuitry the data value in a data register identified by a hit signal after execution of the instruction using the data register.
摘要翻译： 计算机系统包括指令提取电路，解码电路以解码指令并识别要使用的任何寄存器和调度电路，以将指令分派到一个或多个执行单元，所述系统包括用于调试操作的仿真器电路，该仿真器电路被布置为观察数据值在一个 所述计算机电路还包括用于识别要监视的一个或多个寄存器的寄存器手表存储器，用于将由所述解码电路识别的寄存器与在所述寄存器手表存储器中标识的寄存器进行比较的比较器电路，并提供 用于比较中的命中的命中信号，以及响应于命中信号的指令插入电路，将指令序列插入到执行单元中，存储指令存储在由仿真电路可访问的位置中，数据寄存器中的数据值由 执行指导后的命中信号 使用数据寄存器。
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6.发明申请公开(公告)号：US20070174714A1
公开(公告)日：2007-07-26
申请号：US11567990
申请日：2006-12-07
申请人： Renaud Ayrignac , Isabelle Sename , Andrew Cofler
发明人： Renaud Ayrignac , Isabelle Sename , Andrew Cofler
IPC分类号： G06F11/00
CPC分类号： G06F11/3656
摘要： A method for debugging a multitask program executed by a processor includes interrupting the processor during the execution of a task of the program, and activating a debugging mode of the processor, wherein the instructions executed by the processor are supplied by an external emulator. The method comprises steps during which: the processor sends an activation message to the external emulator every time the debugging mode is activated, and upon receiving the activation message, the external emulator sends an acknowledgement message to the processor containing at least one portion of the activation message received.
摘要翻译： 用于调试由处理器执行的多任务程序的方法包括在执行程序的任务期间中断处理器，以及激活处理器的调试模式，其中由处理器执行的指令由外部仿真器提供。 该方法包括以下步骤：在每次调试模式被激活时，处理器向外部仿真器发送激活消息，并且在接收到激活消息时，外部仿真器向处理器发送包含至少一部分激活的确认消息 收到消息。
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公开(公告)号：US06754856B2
公开(公告)日：2004-06-22
申请号：US09748762
申请日：2000-12-22
申请人： Andrew Cofler , Isabelle Sename , Bruno Bernard
发明人： Andrew Cofler , Isabelle Sename , Bruno Bernard
IPC分类号： G06F1100
CPC分类号： G06F9/3865 , G06F9/30072
摘要： A computer system includes instruction fetch circuitry for dispatching fetched instructions to a pipelined execution unit, data memory access circuitry and emulator circuitry for use in debug operations, said emulator circuitry including error indicating circuitry to indicate an error in a data memory access operation, snoop circuitry for snooping memory access operation in said data memory access circuitry, synchronising means for synchronising snooped data memory access addresses with respective program counts for the instructions associated with said access addresses, memory mapped storage circuitry responsive to a data memory access error to indicate the data memory address associated with the error, whereby the emulator circuitry may use the data memory address in a subsequent operation to obtain from the synchronising means the specific program count associated with the memory access operation in which the error occurred.
摘要翻译： 计算机系统包括指令提取电路，用于将读取的指令分派到流水线执行单元，用于调试操作的数据存储器访问电路和仿真器电路，所述仿真器电路包括用于指示数据存储器访问操作中的错误的错误指示电路，窥探电路 用于在所述数据存储器访问电路中窥探存储器访问操作;同步装置，用于将窥探数据存储器访问地址与用于与所述访问地址相关联的指令的相应程序计数同步;存储器映射存储电路，响应于数据存储器访问错误以指示数据存储器 与模拟器电路相关联的地址，由此仿真器电路可以在随后的操作中使用数据存储器地址，以从同步装置获得与发生错误的存储器访问操作相关联的特定程序计数。
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8.发明授权Method and device for debugging a program executed by a multitask processor 有权用于调试由多任务处理器执行的程序的方法和设备公开(公告)号：US07685470B2
公开(公告)日：2010-03-23
申请号：US11567990
申请日：2006-12-07
申请人： Renaud Ayrignac , Isabelle Sename , Andrew Cofler
发明人： Renaud Ayrignac , Isabelle Sename , Andrew Cofler
IPC分类号： G06F11/00
CPC分类号： G06F11/3656
摘要： A method for debugging a multitask program executed by a processor includes interrupting the processor during the execution of a task of the program, and activating a debugging mode of the processor, wherein the instructions executed by the processor are supplied by an external emulator. The method comprises steps during which: the processor sends an activation message to the external emulator every time the debugging mode is activated, and upon receiving the activation message, the external emulator sends an acknowledgement message to the processor containing at least one portion of the activation message received.
摘要翻译： 用于调试由处理器执行的多任务程序的方法包括在执行程序的任务期间中断处理器，以及激活处理器的调试模式，其中由处理器执行的指令由外部仿真器提供。 该方法包括以下步骤：在每次调试模式被激活时，处理器向外部仿真器发送激活消息，并且在接收到激活消息时，外部仿真器向处理器发送包含至少一部分激活的确认消息 收到消息。
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9.发明授权Method and device for saving and restoring a set of registers of a microprocessor in an interruptible manner 有权用于以可中断的方式保存和恢复微处理器的一组寄存器的方法和装置公开(公告)号：US07971040B2
公开(公告)日：2011-06-28
申请号：US11567998
申请日：2006-12-07
申请人： Renaud Ayrignac , Isabelle Sename
发明人： Renaud Ayrignac , Isabelle Sename
CPC分类号： G06F9/4812 , G06F9/30043 , G06F9/3861
摘要： The disclosure relates to a method for executing by a processor an instruction for saving/restoring several internal registers of the processor. The method comprises breaking down the saving/restoring instruction to generate micro-instructions for saving/restoring the content of a register, executing each of the micro-instructions, initializing a progress status of the saving/restoration of the registers, updating the progress status of the saving/restoration upon each generation of a micro-instruction for saving/restoring a register, saving the progress status in the event of an interruption in the saving/restoration of the registers to execute a higher-priority task, and restoring the progress status when the saving/restoration of the registers is resumed.
摘要翻译： 本公开涉及一种用于由处理器执行用于保存/恢复处理器的多个内部寄存器的指令的方法。 该方法包括分解保存/恢复指令以产生用于保存/恢复寄存器的内容的微指令，执行每个微指令，初始化寄存器的保存/恢复进度状态，更新进度状态 在每次生成用于保存/恢复寄存器的微指令时的保存/恢复，在保存/恢复寄存器的中断的情况下保存进度状态以执行更高优先级的任务，并恢复进度 恢复寄存器的保存/恢复时的状态。
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10.发明申请METHOD AND DEVICE FOR SAVING AND RESTORING A SET OF REGISTERS OF A MICROPROCESSOR IN AN INTERRUPTIBLE MANNER 有权用于保存和恢复一组可控制器中微处理器的寄存器的方法和装置公开(公告)号：US20070294517A1
公开(公告)日：2007-12-20
申请号：US11567998
申请日：2006-12-07
申请人： Renaud Ayrignac , Isabelle Sename
发明人： Renaud Ayrignac , Isabelle Sename
IPC分类号： G06F9/30
CPC分类号： G06F9/4812 , G06F9/30043 , G06F9/3861
摘要： The disclosure relates to a method for executing by a processor an instruction for saving/restoring several internal registers of the processor. The method comprises breaking down the saving/restoring instruction to generate micro-instructions for saving/restoring the content of a register, executing each of the micro-instructions, initializing a progress status of the saving/restoration of the registers, updating the progress status of the saving/restoration upon each generation of a micro-instruction for saving/restoring a register, saving the progress status in the event of an interruption in the saving/restoration of the registers to execute a higher-priority task, and restoring the progress status when the saving/restoration of the registers is resumed.
摘要翻译： 本公开涉及一种用于由处理器执行用于保存/恢复处理器的多个内部寄存器的指令的方法。 该方法包括分解保存/恢复指令以产生用于保存/恢复寄存器的内容的微指令，执行每个微指令，初始化寄存器的保存/恢复进度状态，更新进度状态 在每次生成用于保存/恢复寄存器的微指令时的保存/恢复，在保存/恢复寄存器的中断的情况下保存进度状态以执行更高优先级的任务，并恢复进度 恢复寄存器的保存/恢复时的状态。
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