公开(公告)号：US07999817B1

公开(公告)日：2011-08-16

申请号：US11556051

申请日：2006-11-02

申请人： Andrew J. Tao ,  Vimal S. Parikh ,  Yan Yan Tang

发明人： Andrew J. Tao ,  Vimal S. Parikh ,  Yan Yan Tang

IPC分类号： G06T1/60

CPC分类号： G06T1/00

摘要： An apparatus and method for buffering graphics data are described. In one embodiment, a graphics processing apparatus includes a memory and a buffering unit that is connected to the memory. The buffering unit is configured to buffer vertex attributes en route to the memory. The buffering unit is configured to coalesce a subset of the vertex attributes to be stored within a common range of addresses in the memory, and the buffering unit is configured to issue a single write request to the memory on behalf of the subset of the vertex attributes.

摘要翻译： 描述用于缓冲图形数据的装置和方法。 在一个实施例中，图形处理装置包括存储器和连接到存储器的缓冲单元。 缓冲单元被配置为缓冲到存储器的途中的顶点属性。 缓冲单元被配置为将要存储在存储器中的公共地址范围内的顶点属性的子集合并且缓冲单元被配置为代表顶点属性的子集向存储器发出单个写入请求 。

公开(公告)号：US08139071B1

公开(公告)日：2012-03-20

申请号：US11556021

申请日：2006-11-02

申请人： Andrew J. Tao ,  Vimal S. Parikh ,  Yan Yan Tang

发明人： Andrew J. Tao ,  Vimal S. Parikh ,  Yan Yan Tang

IPC分类号： G06T1/60

CPC分类号： G06T1/60

摘要： An apparatus and method for buffering graphics data are described. In one embodiment, a graphics processing apparatus includes a storage unit and a reorder control unit that is connected to the storage unit. The reorder control unit is configured to coordinate storage of vertex attributes in the storage unit so as to convert the vertex attributes from an initial order to a modified order. The reorder control unit is configured to identify a subset of the vertex attributes to be stored within a common range of addresses in the storage unit, and the reorder control unit is configured to access the storage unit such that the subset of the vertex attributes is written into the storage unit substantially in parallel.

摘要翻译： 描述用于缓冲图形数据的装置和方法。 在一个实施例中，图形处理装置包括连接到存储单元的存储单元和重新排序控制单元。 重新排序控制单元被配置为协调存储单元中的顶点属性的存储，以便将顶点属性从初始顺序转换为修改顺序。 重排序控制单元被配置为识别要存储在存储单元中的公共地址范围内的顶点属性的子集，并且重新排序控制单元被配置为访问存储单元，使得顶点属性的子集被写入 基本上并行地进入存储单元。

公开(公告)号：US07542046B1

公开(公告)日：2009-06-02

申请号：US11475599

申请日：2006-06-26

申请人： Lordson L. Yue ,  Vimal S. Parikh ,  Andrew J. Tao

发明人： Lordson L. Yue ,  Vimal S. Parikh ,  Andrew J. Tao

IPC分类号： G06F12/00

CPC分类号： G06T1/60

摘要： An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit, a read-only memory that is connected to the clipping unit, a read-write memory that is connected to the clipping unit, and an addressing unit that is connected to the read-only memory and the read-write memory. The read-only memory is configured to store a clipping program, and the read-write memory is configured to store a patch program. The addressing unit is configured to selectively address one of the read-only memory and the read-write memory based on a set of input conditions.

摘要翻译： 描述用于剪切图形基元的装置，系统和方法。 在一个实施例中，图形处理装置包括剪切单元，连接到剪切单元的只读存储器，连接到剪切单元的读写存储器，以及连接到读取存储器的寻址单元， 只读存储器和读写存储器。 只读存储器被配置为存储剪切程序，并且读写存储器被配置为存储补丁程序。 寻址单元被配置为基于一组输入条件来选择性地寻址只读存储器和读写存储器中的一个。

公开(公告)号：US07466322B1

公开(公告)日：2008-12-16

申请号：US11195389

申请日：2005-08-02

申请人： Henry P. Moreton ,  Vimal S. Parikh ,  Andrew J. Tao

发明人： Henry P. Moreton ,  Vimal S. Parikh ,  Andrew J. Tao

IPC分类号： G09G5/00

CPC分类号： G06T11/40

摘要： Vertices defining a graphics primitive are converted into homogeneous space and clipped against a single clipping plane, the w=0 plane, to produce a clipped graphics primitive having vertices including w coordinates that are greater than or equal to zero. Rasterizing a graphics primitive having a vertex with a w coordinates that is greater than or equal to zero is less complex than rasterizing a graphics primitive having a vertex with a w coordinate that is less than zero. Clipping against the w=0 plane is less complex than conventional clipping since conventional clipping may require that the graphics primitive be clipped against each of the six faces of the viewing frustum to produce a clipped graphics primitive.

摘要翻译： 定义图形基元的顶点被转换成均匀空间，并且相对于单个剪切平面（w = 0平面）被剪切，以产生具有包括大于或等于零的w坐标的顶点的剪切图形基元。 栅格化具有w坐标大于或等于零的顶点的图形原语比光栅化具有小于零的w坐标的顶点的图形基元复杂化。 针对w = 0平面的剪切不如传统的剪裁那样复杂，因为常规的剪裁可能要求将图形原语对准观察平截头体的六个面中的每一个以产生剪切的图形原语。

公开(公告)号：US07292254B1

公开(公告)日：2007-11-06

申请号：US11294791

申请日：2005-12-05

申请人： Lordson L. Yue ,  Vimal S. Parikh ,  Andrew J. Tao

发明人： Lordson L. Yue ,  Vimal S. Parikh ,  Andrew J. Tao

IPC分类号： G09G5/00 ,  G06T1/00

CPC分类号： G06T15/30

摘要： Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a mapping unit and a clipping engine that is connected to the mapping unit. The mapping unit is configured to map a graphics primitive onto a canonical representation. The clipping engine is configured to perform a set of clipping operations with respect to the canonical representation.

摘要翻译： 描述用于剪切图形基元的装置，系统和方法。 在一个实施例中，图形处理装置包括连接到映射单元的映射单元和剪辑引擎。 映射单元被配置为将图形原语映射到规范表示。 剪辑引擎被配置为执行关于规范表示的一组剪切操作。

公开(公告)号：US07705845B1

公开(公告)日：2010-04-27

申请号：US11445726

申请日：2006-06-01

申请人： Vimal S. Parikh ,  Henry Packard Moreton ,  Andrew J. Tao

发明人： Vimal S. Parikh ,  Henry Packard Moreton ,  Andrew J. Tao

IPC分类号： G06T15/40

CPC分类号： G06T15/30

摘要： Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping engine and an output unit connected to the clipping engine. The clipping engine is configured to clip an input graphics primitive with respect to a set of clipping planes to derive spatial attributes of new vertices. The output unit is configured to identify a subset of the new vertices that defines an output graphics primitive, and the output unit is configured to derive non-spatial attributes of the subset of the new vertices to produce the output graphics primitive.

摘要翻译： 描述用于剪切图形基元的装置，系统和方法。 在一个实施例中，图形处理装置包括剪辑引擎和连接到剪辑引擎的输出单元。 剪辑引擎被配置为相对于一组剪切平面剪切输入图形原语以导出新顶点的空间属性。 输出单元被配置为识别限定输出图形基元的新顶点的子集，并且输出单元被配置为导出新顶点的子集的非空间属性以产生输出图形原语。

公开(公告)号：US07616218B1

公开(公告)日：2009-11-10

申请号：US11295355

申请日：2005-12-05

申请人： Vimal S. Parikh ,  Andrew J. Tao ,  Lordson L. Yue

发明人： Vimal S. Parikh ,  Andrew J. Tao ,  Lordson L. Yue

IPC分类号： G09G5/00

CPC分类号： G06F12/1027

摘要： Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a clipping module includes a clipping engine and a clipping controller connected to the clipping engine. The clipping controller is configured to determine which edges of an input graphics primitive intersect a first clipping plane. The clipping controller is configured to direct the clipping engine to clip, with respect to the first clipping plane, a first pair of edges of the input graphics primitive in response to determining that the first pair of edges intersect the first clipping plane.

摘要翻译： 描述用于剪切图形基元的装置，系统和方法。 在一个实施例中，剪辑模块包括剪辑引擎和连接到剪辑引擎的剪辑控制器。 剪辑控制器被配置为确定输入图形基元的哪些边缘与第一剪切平面相交。 剪辑控制器被配置为响应于确定第一对边缘与第一剪切平面相交而引导剪辑引擎相对于第一剪辑平面剪辑输入图形图元的第一对边缘。

公开(公告)号：US09013498B1

公开(公告)日：2015-04-21

申请号：US12340499

申请日：2008-12-19

申请人： John S. Montrym ,  Andrew J. Tao ,  Henry P. Moreton ,  Emmett M. Kilgariff ,  Cass W. Everitt ,  Alexander L. Minkin ,  Eric Anderson ,  Yan Yan Tang ,  Jerome F. Duluk, Jr.

发明人： John S. Montrym ,  Andrew J. Tao ,  Henry P. Moreton ,  Emmett M. Kilgariff ,  Cass W. Everitt ,  Alexander L. Minkin ,  Eric Anderson ,  Yan Yan Tang ,  Jerome F. Duluk, Jr.

IPC分类号： G09G5/00 ,  G09G5/37

CPC分类号： G09G5/37 ,  G06T15/005 ,  G06T15/04 ,  G06T2210/36

摘要： A system and method for tracking and reporting texture map levels of detail that are computed during graphics processing allows for efficient management of texture map storage. Minimum and/or maximum pre-clamped texture map levels of detail values are tracked by a graphics processor and an array stored in memory is updated to report the minimum and/or maximum values for use by an application program. The minimum and/or maximum values may be used to determine the active set of texture map levels of detail that is loaded into graphics memory.

摘要翻译： 用于跟踪和报告在图形处理期间计算的细节纹理图层级的系统和方法允许纹理图存储的有效管理。 图形处理器跟踪细节值的最小和/或最大预夹紧纹理映射级别，更新存储在存储器中的阵列以报告应用程序使用的最小值和/或最大值。 最小值和/或最大值可用于确定加载到图形存储器中的细节的纹理映射级别的活动集合。

公开(公告)号：US08134570B1

公开(公告)日：2012-03-13

申请号：US11532779

申请日：2006-09-18

申请人： Jerome F. Duluk, Jr. ,  Andrew J. Tao ,  Roger L. Allen ,  Svetoslav D. Tzvetkov ,  Yan Yan Tang ,  Elena M. Ing

发明人： Jerome F. Duluk, Jr. ,  Andrew J. Tao ,  Roger L. Allen ,  Svetoslav D. Tzvetkov ,  Yan Yan Tang ,  Elena M. Ing

IPC分类号： G09G5/00

CPC分类号： G06T15/005

摘要： A system, method and computer program product are provided for packing graphics attributes. In use, a plurality of graphics attributes is identified. Such graphics attributes are packed, such that the packed graphics attributes are capable of being processed utilizing a pixel shader.

摘要翻译： 提供了用于打包图形属性的系统，方法和计算机程序产品。 在使用中，识别出多个图形属性。 打包这样的图形属性，使得打包的图形属性能够利用像素着色器进行处理。

公开(公告)号：US06230237B1

公开(公告)日：2001-05-08

申请号：US09150513

申请日：1998-09-09

申请人： Andrew J. Tao ,  Peter D. Robertson

发明人： Andrew J. Tao ,  Peter D. Robertson

IPC分类号： G06F1202

CPC分类号： G06F12/1027 ,  G11C15/00

摘要： A content addressable memory with an internally-timed write operation includes a data input for receiving a input word. Coupled to the data input are a plurality of storage registers comprising stored words. Each storage register includes a comparison circuit for comparing the stored word with the input word and producing therefrom a match output indicating a match when the stored word matches the input word, and indicating a miss when the stored word does not match the input word. Coupled to the storage registers is a miss detector for generating a miss signal responsive to each of the match outputs of the storage registers indicating a miss. Coupled to the miss detector is a write cycle circuit for writing the input word to at least one of the storage registers responsive to receiving the miss signal.

摘要翻译： 具有内部定时写入操作的内容可寻址存储器包括用于接收输入字的数据输入。 耦合到数据输入的是包括存储字的多个存储寄存器。 每个存储寄存器包括比较电路，用于将存储的字与输入字进行比较，从而产生指示所存储的字与输入字匹配时的匹配的匹配输出，并且当所存储的字与输入字不匹配时指示未命中。 耦合到存储寄存器的是错误检测器，用于响应于存储寄存器中的每个匹配输出而产生未命中信号，指示未命中。 耦合到未命中检测器是用于响应于接收到未命中信号而将输入字写入至少一个存储寄存器的写周期电路。